mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-23 14:19:55 -06:00
begin work on the NAND thing
This commit is contained in:
Arisotura
@ -82,7 +82,7 @@ enum
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IRQ_IPCSync,
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IRQ_IPCSendDone,
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IRQ_IPCRecv,
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IRQ_CartSendDone, // TODO: less misleading name
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IRQ_CartXferDone,
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IRQ_CartIREQMC, // IRQ triggered by game cart (example: Pokémon Typing Adventure, BT controller)
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IRQ_GXFIFO,
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IRQ_LidOpen,
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119
src/NDSCart.cpp
119
src/NDSCart.cpp
@ -740,7 +740,7 @@ void CartCommon::ROMCommandFinish(u8* cmd)
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u8 CartCommon::SPIWrite(u8 val, u32 pos, bool last)
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{
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return val;
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return 0xFF;
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}
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void CartCommon::ReadROM(u32 addr, u32 len, u32 offset)
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@ -1159,6 +1159,7 @@ u8 CartRetail::SRAMWrite_FLASH(u8 val, u32 pos, bool last)
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CartRetailNAND::CartRetailNAND(u8* rom, u32 len) : CartRetail(rom, len)
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{
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printf("ohai I am a NAND cart\n");
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}
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CartRetailNAND::~CartRetailNAND()
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@ -1167,6 +1168,9 @@ CartRetailNAND::~CartRetailNAND()
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void CartRetailNAND::Reset()
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{
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SRAMAddr = 0;
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SRAMStatus = 0x20;
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SRAMReadWindow = 0;
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}
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void CartRetailNAND::DoSavestate(Savestate* file)
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@ -1176,44 +1180,103 @@ void CartRetailNAND::DoSavestate(Savestate* file)
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void CartRetailNAND::ROMCommandStart(u8* cmd)
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{
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// ROM header 94/96 = save addr start / 0x20000
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switch (cmd[0])
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{
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case 0x85: // write enable?
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SRAMStatus |= (1<<4);
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break;
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case 0x8B: // revert to ROM read mode
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SRAMReadWindow = 0;
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break;
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case 0x94: // return ID data
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{
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// TODO: check what the data really is. probably the NAND chip's ID.
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// also, might be different between different games or even between different carts.
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// this was taken from a Jam with the Band cart.
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// not that the game seems to really use this for anything.
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u8 iddata[0x30] =
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{
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0xEC, 0xF1, 0x00, 0x95, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x9E, 0xA1, 0x51, 0x65, 0x34, 0x35,
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0x30, 0x35, 0x30, 0x31, 0x19, 0x19, 0x02, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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};
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memset(TransferData, 0, TransferLen);
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memcpy(TransferData, iddata, std::min(TransferLen, 0x30u));
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}
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break;
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case 0xB2: // set window for reading SRAM
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{
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u32 addr = (cmd[1]<<24) | ((cmd[2]&0xFE)<<16);
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// window is 0x20000 bytes, address is aligned to that boundary
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// NAND remains stuck 'busy' forever if this is less than the starting SRAM address
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// TODO.
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SRAMReadWindow = addr;
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}
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break;
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case 0xB7:
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{
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u32 addr = (cmd[1]<<24) | (cmd[2]<<16) | (cmd[3]<<8) | cmd[4];
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memset(TransferData, 0, TransferLen);
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if (((addr + TransferLen - 1) >> 12) != (addr >> 12))
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if (SRAMReadWindow == 0)
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{
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u32 len1 = 0x1000 - (addr & 0xFFF);
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ReadROM_B7(addr, len1, 0);
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ReadROM_B7(addr+len1, TransferLen-len1, len1);
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memset(TransferData, 0, TransferLen);
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if (((addr + TransferLen - 1) >> 12) != (addr >> 12))
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{
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u32 len1 = 0x1000 - (addr & 0xFFF);
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ReadROM_B7(addr, len1, 0);
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ReadROM_B7(addr+len1, TransferLen-len1, len1);
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}
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else
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ReadROM_B7(addr, TransferLen, 0);
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}
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else
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ReadROM_B7(addr, TransferLen, 0);
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}
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break;
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case 0xC0: // SD read
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{
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u32 sector = (cmd[1]<<24) | (cmd[2]<<16) | (cmd[3]<<8) | cmd[4];
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u64 addr = sector * 0x200ULL;
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if (CartSD)
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{
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fseek(CartSD, addr, SEEK_SET);
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fread(TransferData, TransferLen, 1, CartSD);
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memset(TransferData, 0xFF, TransferLen);
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u32 sramstart = *(u16*)&ROM[0x96] << 17;
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u32 sramend = sramstart + 0x800000; // CHECKME
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if (SRAMReadWindow >= sramstart && SRAMReadWindow < sramend &&
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addr >= SRAMReadWindow && addr < (SRAMReadWindow+0x20000))
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{
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// TODO!!
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if (addr == (sramstart+0x7FF800))
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{
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u8 iddata[0x10] = {0xEC, 0x00, 0x9E, 0xA1, 0x51, 0x65, 0x34, 0x35, 0x30, 0x35, 0x30, 0x31, 0x19, 0x19, 0x02, 0x0A};
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memcpy(TransferData, iddata, std::min(TransferLen, 0x10u));
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printf("READING ID BLOCK @ %08X\n", addr);
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}
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}
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}
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}
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break;
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case 0xC1: // SD write
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case 0xD6: // read NAND status
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{
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TransferDir = 1;
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// status bits
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// bit5: ready
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// bit4: write enable
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printf("NAND STATUS %02X\n", SRAMStatus);
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for (u32 i = 0; i < TransferLen; i+=4)
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*(u32*)&TransferData[i] = SRAMStatus * 0x01010101;
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}
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break;
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default:
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/*if (cmd[0] != 0xB8)
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printf("shitty command %02X %02X %02X %02X %02X %02X %02X %02X - %08X\n",
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cmd[0], cmd[1], cmd[2], cmd[3],
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cmd[4], cmd[5], cmd[6], cmd[7], TransferLen);*/
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return CartRetail::ROMCommandStart(cmd);
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}
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}
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@ -1231,7 +1294,7 @@ void CartRetailNAND::ROMCommandFinish(u8* cmd)
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u8 CartRetailNAND::SPIWrite(u8 val, u32 pos, bool last)
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{
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return val;
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return 0xFF;
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}
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@ -1653,6 +1716,11 @@ bool LoadROMCommon(u32 filelength, const char *sram, bool direct)
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if (CartIsDSi)
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CartID |= 0x40000000;
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// cart ID for Jam with the Band
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// TODO: this kind of ID triggers different KEY1 phase
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// (repeats commands a bunch of times)
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//CartID = 0x88017FEC;
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printf("Cart ID: %08X\n", CartID);
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u32 arm9base = *(u32*)&CartROM[0x20];
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@ -1712,6 +1780,8 @@ bool LoadROMCommon(u32 filelength, const char *sram, bool direct)
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else
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Cart = new CartRetail(CartROM, CartROMSize);
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if (Cart) Cart->Reset();
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// encryption
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Key1_InitKeycode(false, gamecode, 2, 2);
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@ -1864,7 +1934,7 @@ void ROMEndTransfer(u32 param)
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ROMCnt &= ~(1<<31);
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if (SPICnt & (1<<14))
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NDS::SetIRQ((NDS::ExMemCnt[0]>>11)&0x1, NDS::IRQ_CartSendDone);
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NDS::SetIRQ((NDS::ExMemCnt[0]>>11)&0x1, NDS::IRQ_CartXferDone);
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/*if (TransferDir == 1)
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{
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@ -2095,11 +2165,11 @@ void WriteROMCnt(u32 val)
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*(u32*)&TransferCmd[4] = *(u32*)&ROMCommand[4];
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}
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/*printf("ROM COMMAND %04X %08X %02X%02X%02X%02X%02X%02X%02X%02X SIZE %04X\n",
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printf("ROM COMMAND %04X %08X %02X%02X%02X%02X%02X%02X%02X%02X SIZE %04X\n",
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SPICnt, ROMCnt,
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TransferCmd[0], TransferCmd[1], TransferCmd[2], TransferCmd[3],
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TransferCmd[4], TransferCmd[5], TransferCmd[6], TransferCmd[7],
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datasize);*/
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datasize);
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// default is read
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// commands that do writes will change this
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@ -2195,6 +2265,7 @@ void WriteROMCnt(u32 val)
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u32 cmddelay = 8;
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// delays are only applied when the WR bit is cleared
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// CHECKME: do the delays apply at the end (instead of start) when WR is set?
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if (!(ROMCnt & (1<<30)))
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{
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cmddelay += (ROMCnt & 0x1FFF);
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@ -148,6 +148,9 @@ public:
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void ROMCommandFinish(u8* cmd);
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u8 SPIWrite(u8 val, u32 pos, bool last);
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private:
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u32 SRAMReadWindow;
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};
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// CartRetailIR -- SPI IR device and SRAM
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