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DSi: add support for SCFG_EXT bit 13 (32-bit VRAM bus)

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Arisotura
2025-07-07 02:47:46 +02:00
parent 2cb07bf126
commit 85dcf65231
2 changed files with 26 additions and 1 deletions
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25
src/DSi.cpp
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@ -175,6 +175,8 @@ void DSi::Reset()
// LCD init flag
GPU.DispStat[0] |= (1<<6);
GPU.DispStat[1] |= (1<<6);
UpdateVRAMTimings();
}
void DSi::Stop(Platform::StopReason reason)
@ -285,6 +287,8 @@ void DSi::DoSavestateExtra(Savestate* file)
I2C.DoSavestate(file);
SDMMC.DoSavestate(file);
SDIO.DoSavestate(file);
UpdateVRAMTimings();
}
void DSi::SetCartInserted(bool inserted)
@ -666,6 +670,8 @@ void DSi::SetupDirectBoot()
ARM9.CP15Write(0x671, 0x02FFC01B);
ARM9.CP15Write(0x910, 0x0E00000A);
ARM9.CP15Write(0x911, 0x00000020);
UpdateVRAMTimings();
}
void DSi::SoftReset()
@ -717,10 +723,11 @@ void DSi::SoftReset()
SCFG_RST = 0;
DSP.SetRstLine(false);
// LCD init flag
GPU.DispStat[0] |= (1<<6);
GPU.DispStat[1] |= (1<<6);
UpdateVRAMTimings();
}
bool DSi::LoadNAND()
@ -1252,6 +1259,20 @@ void DSi::MapNWRAMRange(u32 cpu, u32 num, u32 val)
}
}
void DSi::UpdateVRAMTimings()
{
if (SCFG_EXT[0] & (1<<13))
{
SetARM9RegionTimings(0x06000, 0x07000, Mem9_VRAM, 32, 1, 1);
SetARM7RegionTimings(0x06000, 0x07000, Mem7_VRAM, 32, 1, 1);
}
else
{
SetARM9RegionTimings(0x06000, 0x07000, Mem9_VRAM, 16, 1, 1);
SetARM7RegionTimings(0x06000, 0x07000, Mem7_VRAM, 16, 1, 1);
}
}
void DSi::ApplyNewRAMSize(u32 size)
{
switch (size)
@ -2565,6 +2586,8 @@ void DSi::ARM9IOWrite32(u32 addr, u32 val)
//if (newram != oldram)
// NDS::ScheduleEvent(NDS::Event_DSi_RAMSizeChange, false, 512*512*512, ApplyNewRAMSize, newram);
Log(LogLevel::Debug, "from %08X, ARM7 %08X, %08X\n", NDS::GetPC(0), NDS::GetPC(1), ARM7.R[1]);
UpdateVRAMTimings();
}
return;

2
src/DSi.h
View File

@ -97,6 +97,8 @@ public:
void MapNWRAM_C(u32 num, u8 val);
void MapNWRAMRange(u32 cpu, u32 num, u32 val);
void UpdateVRAMTimings();
u8 ARM9Read8(u32 addr) override;
u16 ARM9Read16(u32 addr) override;
u32 ARM9Read32(u32 addr) override;