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misaligned pc..........

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This commit is contained in:
Jaklyy 2024-09-20 23:47:40 -04:00
parent 157e9c5b04
commit 8d451dff48
1 changed files with 16 additions and 9 deletions
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25
src/ARM.cpp
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@ -837,6 +837,7 @@ void ARMv4::Execute()
{
// attempt to delay t bit changes without a pipeline flush (msr) by one instruction
Thumb = CPSR & 0x20;
bool fix = !Thumb;
if constexpr (mode == CPUExecuteMode::InterpreterGDB)
GdbCheckC();
@ -845,17 +846,17 @@ void ARMv4::Execute()
// but if the code fetch takes more than 1 cycle(?) it can take effect early for just the code fetch
if (!Thumb && (NDS.ARM7MemTimings[CodeCycles][2] > 1)) [[unlikely]] // checkme
{
R[15] = (R[15] + 4) & ~0x3;
R[15] += 4;
CurInstr = NextInstr[0];
NextInstr[0] = NextInstr[1];
NextInstr[1] = CodeRead32(R[15]);
NextInstr[1] = CodeRead32(R[15] & ~3);
}
else
else [[likely]]
{
R[15] += 2;
CurInstr = NextInstr[0];
NextInstr[0] = NextInstr[1];
NextInstr[1] = CodeRead16(R[15]);
NextInstr[1] = CodeRead16(R[15] & ~1);
}
if (IRQ && !(CPSR & 0x80)) TriggerIRQ<mode>();
@ -865,6 +866,12 @@ void ARMv4::Execute()
u32 icode = (CurInstr >> 6) & 0x3FF;
ARMInterpreter::THUMBInstrTable[icode](this);
}
if (fix) [[unlikely]] // attempt at fixing flushless t bit changes
{
R[15] += 2; // yes it can end up misaligned. that's correct.
NextInstr[1] = CodeRead32(R[15] & ~3);
}
}
else
{
@ -878,17 +885,17 @@ void ARMv4::Execute()
// but if the code fetch takes more than 1 cycle(?) it can take effect early for just the code fetch
if (Thumb && (NDS.ARM7MemTimings[CodeCycles][2] > 1)) [[unlikely]] // checkme?
{
R[15] = (R[15] + 4) & ~0x3;
R[15] += 4;
CurInstr = NextInstr[0];
NextInstr[0] = NextInstr[1];
NextInstr[1] = CodeRead16(R[15]);
NextInstr[1] = CodeRead16(R[15] & ~1);
}
else
else [[likely]]
{
R[15] = (R[15] + 4) & ~0x3;
R[15] += 4;
CurInstr = NextInstr[0];
NextInstr[0] = NextInstr[1];
NextInstr[1] = CodeRead32(R[15]);
NextInstr[1] = CodeRead32(R[15] & ~3);
}
if (IRQ && !(CPSR & 0x80)) TriggerIRQ<mode>();