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https://github.com/melonDS-emu/melonDS.git
synced 2024-11-14 13:27:41 -07:00
implement cmp with "rd == 15" on arm9
cmp and friends with bits 12-15 set to 1 borrow characteristics from their legacy 26 bit p variants thumb version does nothing of note
This commit is contained in:
Jaklyy
parent
3870216fd0
commit
93dce82b07
@ -141,7 +141,7 @@ void A_MSR_IMM(ARM* cpu)
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{
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if (cpu->CurInstr & (1<<22))
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{
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cpu->AddCycles_CI(2); // spsr_fsxc
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cpu->AddCycles_CI(2); // spsr
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}
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else if (cpu->CurInstr & (0x7<<16)) cpu->AddCycles_CI(2); // cpsr_sxc
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else cpu->AddCycles_C();
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@ -211,7 +211,7 @@ void A_MSR_REG(ARM* cpu)
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{
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if (cpu->CurInstr & (1<<22))
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{
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cpu->AddCycles_CI(2); // spsr_fsxc
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cpu->AddCycles_CI(2); // spsr
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}
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else if (cpu->CurInstr & (0x7<<16)) cpu->AddCycles_CI(2); // cpsr_sxc
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else cpu->AddCycles_C();
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@ -581,12 +581,12 @@ A_IMPLEMENT_ALU_OP(RSC,)
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#define A_TST(c) \
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u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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u32 res = a & b; \
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cpu->SetNZ(res & 0x80000000, \
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!res); \
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if (((cpu->CurInstr>>12) & 0xF) == 15) [[unlikely]] /* yes this instruction has a secret rd for some reason */ \
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if (((cpu->CurInstr>>12) & 0xF) == 15) [[unlikely]] /* this seems to trigger alu rd==15 behavior for arm7 and legacy instruction behavior for arm9 */ \
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{ \
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if (cpu->Num == 1) \
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{ \
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cpu->SetNZ(res & 0x80000000, \
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!res); \
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u32 oldpsr = cpu->CPSR; \
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cpu->RestoreCPSR(); /* ARM7TDMI restores cpsr and does ___not___ flush the pipeline. */ \
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if (cpu->CPSR & 0x20) \
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@ -595,7 +595,12 @@ A_IMPLEMENT_ALU_OP(RSC,)
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cpu->CPSR &= ~0x20; /* keep it from crashing the emulator at least */ \
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} \
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} \
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else Platform::Log(Platform::LogLevel::Warn, "UNIMPLEMENTED: TST w/ rd == 15 on ARM9\n"); \
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else cpu->JumpTo(res & ~1, true); /* TSTP dna, doesn't update flags */ \
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} \
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else \
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{ \
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cpu->SetNZ(res & 0x80000000, \
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!res); \
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} \
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if (c) cpu->AddCycles_CI(c); else cpu->AddCycles_C();
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@ -605,12 +610,12 @@ A_IMPLEMENT_ALU_TEST(TST,_S)
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#define A_TEQ(c) \
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u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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u32 res = a ^ b; \
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cpu->SetNZ(res & 0x80000000, \
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!res); \
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if (((cpu->CurInstr>>12) & 0xF) == 15) [[unlikely]] /* yes this instruction has a secret rd for some reason */ \
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if (((cpu->CurInstr>>12) & 0xF) == 15) [[unlikely]] /* this seems to trigger alu rd==15 behavior for arm7 and legacy instruction behavior for arm9 */ \
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{ \
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if (cpu->Num == 1) \
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{ \
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cpu->SetNZ(res & 0x80000000, \
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!res); \
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u32 oldpsr = cpu->CPSR; \
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cpu->RestoreCPSR(); /* ARM7TDMI restores cpsr and does ___not___ flush the pipeline. */ \
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if (cpu->CPSR & 0x20) \
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@ -619,7 +624,12 @@ A_IMPLEMENT_ALU_TEST(TST,_S)
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cpu->CPSR &= ~0x20; /* keep it from crashing the emulator at least */ \
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} \
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} \
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else Platform::Log(Platform::LogLevel::Warn, "UNIMPLEMENTED: TEQ w/ rd == 15 on ARM9\n"); \
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else cpu->JumpTo(res & ~1, true); /* TEQP dna, doesn't update flags */ \
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} \
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else \
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{ \
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cpu->SetNZ(res & 0x80000000, \
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!res); \
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} \
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if (c) cpu->AddCycles_CI(c); else cpu->AddCycles_C();
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@ -629,14 +639,14 @@ A_IMPLEMENT_ALU_TEST(TEQ,_S)
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#define A_CMP(c) \
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u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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u32 res = a - b; \
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cpu->SetNZCV(res & 0x80000000, \
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!res, \
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CarrySub(a, b), \
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OverflowSub(a, b)); \
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if (((cpu->CurInstr>>12) & 0xF) == 15) [[unlikely]] /* yes this instruction has a secret rd for some reason */ \
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if (((cpu->CurInstr>>12) & 0xF) == 15) [[unlikely]] /* this seems to trigger alu rd==15 behavior for arm7 and legacy instruction behavior for arm9 */ \
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{ \
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if (cpu->Num == 1) \
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{ \
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cpu->SetNZCV(res & 0x80000000, \
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!res, \
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CarrySub(a, b), \
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OverflowSub(a, b)); \
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u32 oldpsr = cpu->CPSR; \
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cpu->RestoreCPSR(); /* ARM7TDMI restores cpsr and does ___not___ flush the pipeline. */ \
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if (cpu->CPSR & 0x20) \
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@ -645,7 +655,14 @@ A_IMPLEMENT_ALU_TEST(TEQ,_S)
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cpu->CPSR &= ~0x20; /* keep it from crashing the emulator at least */ \
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} \
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} \
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else Platform::Log(Platform::LogLevel::Warn, "UNIMPLEMENTED: CMP w/ rd == 15 on ARM9\n"); \
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else cpu->JumpTo(res & ~1, true); /* CMPP dna, doesn't update flags */ \
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} \
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else \
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{ \
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cpu->SetNZCV(res & 0x80000000, \
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!res, \
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CarrySub(a, b), \
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OverflowSub(a, b)); \
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} \
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if (c) cpu->AddCycles_CI(c); else cpu->AddCycles_C();
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@ -655,14 +672,14 @@ A_IMPLEMENT_ALU_TEST(CMP,)
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#define A_CMN(c) \
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u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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u32 res = a + b; \
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cpu->SetNZCV(res & 0x80000000, \
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!res, \
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CarryAdd(a, b), \
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OverflowAdd(a, b)); \
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if (((cpu->CurInstr>>12) & 0xF) == 15) [[unlikely]] /* yes this instruction has a secret rd for some reason */ \
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if (((cpu->CurInstr>>12) & 0xF) == 15) [[unlikely]] /* this seems to trigger alu rd==15 behavior for arm7 and legacy instruction behavior for arm9 */ \
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{ \
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if (cpu->Num == 1) \
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{ \
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cpu->SetNZCV(res & 0x80000000, \
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!res, \
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CarryAdd(a, b), \
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OverflowAdd(a, b)); \
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u32 oldpsr = cpu->CPSR; \
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cpu->RestoreCPSR(); /* ARM7TDMI restores cpsr and does ___not___ flush the pipeline. */ \
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if (cpu->CPSR & 0x20) \
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@ -671,7 +688,14 @@ A_IMPLEMENT_ALU_TEST(CMP,)
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cpu->CPSR &= ~0x20; /* keep it from crashing the emulator at least */ \
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} \
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} \
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else Platform::Log(Platform::LogLevel::Warn, "UNIMPLEMENTED: CMN w/ rd == 15 on ARM9\n"); \
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else cpu->JumpTo(res & ~1, true); /* CMNP dna, doesn't update flags */ \
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} \
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else \
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{ \
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cpu->SetNZCV(res & 0x80000000, \
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!res, \
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CarryAdd(a, b), \
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OverflowAdd(a, b)); \
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} \
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if (c) cpu->AddCycles_CI(c); else cpu->AddCycles_C();
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@ -1625,20 +1649,18 @@ void T_CMP_HIREG(ARM* cpu)
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!res,
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CarrySub(a, b),
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OverflowSub(a, b));
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if (rd == 15) [[unlikely]]
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if ((cpu->Num == 1) && (rd == 15))
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{
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if (cpu->Num == 1)
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u32 oldpsr = cpu->CPSR;
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cpu->RestoreCPSR(); // ARM7TDMI restores cpsr and does ___not___ flush the pipeline.
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if (!(cpu->CPSR & 0x20))
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{
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u32 oldpsr = cpu->CPSR;
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cpu->RestoreCPSR(); // ARM7TDMI restores cpsr and does ___not___ flush the pipeline.
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if (!(cpu->CPSR & 0x20))
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{
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Platform::Log(Platform::LogLevel::Warn, "UNIMPLEMENTED: MSR REG T bit change on ARM7\n");
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cpu->CPSR |= 0x20; // keep it from crashing the emulator at least
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}
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Platform::Log(Platform::LogLevel::Warn, "UNIMPLEMENTED: MSR REG T bit change on ARM7\n");
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cpu->CPSR |= 0x20; // keep it from crashing the emulator at least
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}
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else Platform::Log(Platform::LogLevel::Warn, "UNIMPLEMENTED: CMP HIREG w/ rd == 15 on ARM9\n");
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}
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cpu->AddCycles_C();
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}
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