mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2024-11-14 21:37:42 -07:00
decrease jit block cache address granularity
fixes Dragon Quest IX move code with side effects out of assert, fixes release build (thanks to m4wx for this one) also remove some leftovers of jit pipelining
This commit is contained in:
RSDuck
parent
52dd0ee75a
commit
9cf7780e46
@ -106,7 +106,7 @@ u32 AddrTranslate9[0x2000];
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u32 AddrTranslate7[0x4000];
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JitBlockEntry FastBlockAccess[ExeMemSpaceSize / 2];
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AddressRange CodeRanges[ExeMemSpaceSize / 256];
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AddressRange CodeRanges[ExeMemSpaceSize / 512];
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TinyVector<JitBlock*> JitBlocks;
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JitBlock* RestoreCandidates[0x1000] = {NULL};
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@ -285,6 +285,13 @@ InterpreterFunc InterpretARM[ARMInstrInfo::ak_Count] =
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#undef F_MEM_HD
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#undef F
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void T_BL_LONG(ARM* cpu)
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{
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ARMInterpreter::T_BL_LONG_1(cpu);
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cpu->R[15] += 2;
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ARMInterpreter::T_BL_LONG_2(cpu);
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}
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#define F(x) ARMInterpreter::T_##x
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InterpreterFunc InterpretTHUMB[ARMInstrInfo::tk_Count] =
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{
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@ -302,7 +309,7 @@ InterpreterFunc InterpretTHUMB[ARMInstrInfo::tk_Count] =
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F(PUSH), F(POP), F(LDMIA), F(STMIA),
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F(BCOND), F(BX), F(BLX_REG), F(B), F(BL_LONG_1), F(BL_LONG_2),
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F(UNK), F(SVC),
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NULL // BL_LONG psudo opcode
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T_BL_LONG // BL_LONG psudo opcode
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};
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#undef F
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@ -341,7 +348,7 @@ void CompileBlock(ARM* cpu)
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JIT_DEBUGPRINT("start block %x (%x) %p %p (region invalidates %dx)\n",
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blockAddr, pseudoPhysicalAddr, FastBlockAccess[pseudoPhysicalAddr / 2],
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cpu->Num == 0 ? LookUpBlock<0>(blockAddr) : LookUpBlock<1>(blockAddr),
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CodeRanges[pseudoPhysicalAddr / 256].TimesInvalidated);
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CodeRanges[pseudoPhysicalAddr / 512].TimesInvalidated);
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u32 lastSegmentStart = blockAddr;
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@ -352,7 +359,7 @@ void CompileBlock(ARM* cpu)
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instrs[i].BranchFlags = 0;
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instrs[i].SetFlags = 0;
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instrs[i].Instr = nextInstr[0];
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instrs[i].NextInstr[0] = nextInstr[0] = nextInstr[1];
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nextInstr[0] = nextInstr[1];
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instrs[i].Addr = nextInstrAddr[0];
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nextInstrAddr[0] = nextInstrAddr[1];
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@ -361,7 +368,7 @@ void CompileBlock(ARM* cpu)
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u32 translatedAddr = (cpu->Num == 0
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? TranslateAddr<0>(instrs[i].Addr)
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: TranslateAddr<1>(instrs[i].Addr)) & ~0xFF;
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: TranslateAddr<1>(instrs[i].Addr)) & ~0x1FF;
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if (i == 0 || translatedAddr != addresseRanges[numAddressRanges - 1])
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{
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bool returning = false;
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@ -400,7 +407,6 @@ void CompileBlock(ARM* cpu)
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nextInstr[1] = cpuv4->CodeRead32(r15);
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instrs[i].CodeCycles = cpu->CodeCycles;
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}
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instrs[i].NextInstr[1] = nextInstr[1];
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instrs[i].Info = ARMInstrInfo::Decode(thumb, cpu->Num, instrs[i].Instr);
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cpu->R[15] = r15;
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@ -584,7 +590,7 @@ void CompileBlock(ARM* cpu)
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for (int j = 0; j < numAddressRanges; j++)
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{
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assert(addresseRanges[j] == block->AddressRanges()[j]);
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CodeRanges[addresseRanges[j] / 256].Blocks.Add(block);
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CodeRanges[addresseRanges[j] / 512].Blocks.Add(block);
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}
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FastBlockAccess[block->PseudoPhysicalAddr / 2] = block->EntryPoint;
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@ -595,7 +601,7 @@ void CompileBlock(ARM* cpu)
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void InvalidateByAddr(u32 pseudoPhysical)
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{
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JIT_DEBUGPRINT("invalidating by addr %x\n", pseudoPhysical);
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AddressRange* range = &CodeRanges[pseudoPhysical / 256];
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AddressRange* range = &CodeRanges[pseudoPhysical / 512];
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int startLength = range->Blocks.Length;
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for (int i = 0; i < range->Blocks.Length; i++)
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{
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@ -604,15 +610,17 @@ void InvalidateByAddr(u32 pseudoPhysical)
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for (int j = 0; j < block->NumAddresses; j++)
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{
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u32 addr = block->AddressRanges()[j];
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if ((addr / 256) != (pseudoPhysical / 256))
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if ((addr / 512) != (pseudoPhysical / 512))
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{
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AddressRange* otherRange = &CodeRanges[addr / 256];
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AddressRange* otherRange = &CodeRanges[addr / 512];
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assert(otherRange != range);
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assert(otherRange->Blocks.RemoveByValue(block));
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bool removed = otherRange->Blocks.RemoveByValue(block);
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assert(removed);
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}
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}
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assert(JitBlocks.RemoveByValue(block));
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bool removed = JitBlocks.RemoveByValue(block);
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assert(removed);
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FastBlockAccess[block->PseudoPhysicalAddr / 2] = NULL;
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@ -631,14 +639,14 @@ void InvalidateByAddr(u32 pseudoPhysical)
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void InvalidateByAddr7(u32 addr)
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{
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u32 pseudoPhysical = TranslateAddr<1>(addr);
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if (__builtin_expect(CodeRanges[pseudoPhysical / 256].Blocks.Length > 0, false))
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if (__builtin_expect(CodeRanges[pseudoPhysical / 512].Blocks.Length > 0, false))
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InvalidateByAddr(pseudoPhysical);
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}
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void InvalidateITCM(u32 addr)
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{
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u32 pseudoPhysical = addr + ExeMemRegionOffsets[exeMem_ITCM];
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if (CodeRanges[pseudoPhysical / 256].Blocks.Length > 0)
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if (CodeRanges[pseudoPhysical / 512].Blocks.Length > 0)
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InvalidateByAddr(pseudoPhysical);
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}
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@ -654,7 +662,7 @@ void InvalidateAll()
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for (int j = 0; j < block->NumAddresses; j++)
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{
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u32 addr = block->AddressRanges()[j];
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AddressRange* range = &CodeRanges[addr / 256];
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AddressRange* range = &CodeRanges[addr / 512];
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range->Blocks.Clear();
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if (range->TimesInvalidated + 1 > range->TimesInvalidated)
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range->TimesInvalidated++;
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@ -689,8 +697,8 @@ void ResetBlockCache()
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for (int j = 0; j < block->NumAddresses; j++)
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{
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u32 addr = block->AddressRanges()[j];
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CodeRanges[addr / 256].Blocks.Clear();
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CodeRanges[addr / 256].TimesInvalidated = 0;
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CodeRanges[addr / 512].Blocks.Clear();
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CodeRanges[addr / 512].TimesInvalidated = 0;
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}
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delete block;
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}
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@ -38,7 +38,6 @@ struct FetchedInstr
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u8 BranchFlags;
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u8 SetFlags;
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u32 Instr;
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u32 NextInstr[2];
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u32 Addr;
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u8 CodeCycles;
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@ -185,7 +184,7 @@ struct __attribute__((packed)) AddressRange
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u16 TimesInvalidated;
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};
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extern AddressRange CodeRanges[ExeMemSpaceSize / 256];
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extern AddressRange CodeRanges[ExeMemSpaceSize / 512];
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typedef void (*InterpreterFunc)(ARM* cpu);
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extern InterpreterFunc InterpretARM[];
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@ -105,7 +105,7 @@ void* Compiler::Gen_MemoryRoutine9(bool store, int size)
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static_assert(sizeof(AddressRange) == 16);
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LEA(32, ABI_PARAM1, MDisp(ABI_PARAM3, ExeMemRegionOffsets[exeMem_ITCM]));
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MOV(32, R(RSCRATCH), R(ABI_PARAM1));
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SHR(32, R(RSCRATCH), Imm8(8));
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SHR(32, R(RSCRATCH), Imm8(9));
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SHL(32, R(RSCRATCH), Imm8(4));
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CMP(32, MDisp(RSCRATCH, squeezePointer(CodeRanges) + offsetof(AddressRange, Blocks.Length)), Imm8(0));
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FixupBranch noCode = J_CC(CC_Z);
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@ -203,7 +203,7 @@ void* Compiler::Gen_MemoryRoutineSeq9(bool store, bool preinc)
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ADD(32, R(RSCRATCH), Imm32(ExeMemRegionOffsets[exeMem_ITCM]));
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MOV(32, R(ABI_PARAM4), R(RSCRATCH));
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SHR(32, R(RSCRATCH), Imm8(8));
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SHR(32, R(RSCRATCH), Imm8(9));
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SHL(32, R(RSCRATCH), Imm8(4));
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CMP(32, MDisp(RSCRATCH, squeezePointer(CodeRanges) + offsetof(AddressRange, Blocks.Length)), Imm8(0));
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FixupBranch noCode = J_CC(CC_Z);
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@ -284,28 +284,29 @@ void fault(u32 a, u32 b)
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void Compiler::Comp_MemAccess(int rd, int rn, const ComplexOperand& op2, int size, int flags)
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{
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if (flags & memop_Store)
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{
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Comp_AddCycles_CD();
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}
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else
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{
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Comp_AddCycles_CDI();
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}
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u32 addressMask = ~0;
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if (size == 32)
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addressMask = ~3;
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if (size == 16)
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addressMask = ~1;
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if (rn == 15 && rd != 15 && op2.IsImm && !(flags & (memop_Post|memop_Store|memop_Writeback)))
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if (rn == 15 && rd != 15 && op2.IsImm && !(flags & (memop_SignExtend|memop_Post|memop_Store|memop_Writeback)))
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{
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Comp_MemLoadLiteral(size, rd,
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R15 + op2.Imm * ((flags & memop_SubtractOffset) ? -1 : 1));
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u32 addr = R15 + op2.Imm * ((flags & memop_SubtractOffset) ? -1 : 1);
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Comp_MemLoadLiteral(size, rd, addr);
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return;
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}
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else
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{
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if (flags & memop_Store)
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{
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Comp_AddCycles_CD();
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}
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else
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{
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Comp_AddCycles_CDI();
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}
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OpArg rdMapped = MapReg(rd);
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OpArg rnMapped = MapReg(rn);
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@ -5,7 +5,7 @@
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namespace ARMInstrInfo
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{
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#define ak(x) ((x) << 21)
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#define ak(x) ((x) << 22)
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enum {
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A_Read0 = 1 << 0,
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@ -36,7 +36,8 @@ enum {
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A_StaticShiftSetC = 1 << 18,
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A_SetC = 1 << 19,
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A_WriteMem = 1 << 20
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A_WriteMem = 1 << 20,
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A_LoadMem = 1 << 21
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};
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#define A_BIOP A_Read16
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@ -122,7 +123,7 @@ const u32 A_QSUB = A_Write12 | A_Read0 | A_Read16 | A_UnkOnARM7 | ak(ak_QSUB);
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const u32 A_QDADD = A_Write12 | A_Read0 | A_Read16 | A_UnkOnARM7 | ak(ak_QDADD);
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const u32 A_QDSUB = A_Write12 | A_Read0 | A_Read16 | A_UnkOnARM7 | ak(ak_QDSUB);
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#define A_LDR A_Write12
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#define A_LDR A_Write12 | A_LoadMem
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#define A_STR A_Read12 | A_WriteMem
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#define A_IMPLEMENT_WB_LDRSTR(x,k) \
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@ -143,7 +144,7 @@ A_IMPLEMENT_WB_LDRSTR(STRB,STR)
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A_IMPLEMENT_WB_LDRSTR(LDR,LDR)
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A_IMPLEMENT_WB_LDRSTR(LDRB,LDR)
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#define A_LDRD A_Write12Double
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#define A_LDRD A_Write12Double | A_LoadMem
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#define A_STRD A_Read12Double | A_WriteMem
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#define A_IMPLEMENT_HD_LDRSTR(x,k) \
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@ -159,10 +160,10 @@ A_IMPLEMENT_HD_LDRSTR(LDRH,LDR)
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A_IMPLEMENT_HD_LDRSTR(LDRSB,LDR)
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A_IMPLEMENT_HD_LDRSTR(LDRSH,LDR)
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const u32 A_SWP = A_Write12 | A_Read16 | A_Read0 | A_WriteMem | ak(ak_SWP);
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const u32 A_SWPB = A_Write12 | A_Read16 | A_Read0 | A_WriteMem | ak(ak_SWPB);
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const u32 A_SWP = A_Write12 | A_Read16 | A_Read0 | A_LoadMem | A_WriteMem | ak(ak_SWP);
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const u32 A_SWPB = A_Write12 | A_Read16 | A_Read0 | A_LoadMem | A_WriteMem | ak(ak_SWPB);
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const u32 A_LDM = A_Read16 | A_MemWriteback | ak(ak_LDM);
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const u32 A_LDM = A_Read16 | A_MemWriteback | A_LoadMem | ak(ak_LDM);
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const u32 A_STM = A_Read16 | A_MemWriteback | A_WriteMem | ak(ak_STM);
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const u32 A_B = A_BranchAlways | ak(ak_B);
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@ -360,6 +361,9 @@ Info Decode(bool thumb, u32 num, u32 instr)
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if (data & T_WriteMem)
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res.SpecialKind = special_WriteMem;
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if (res.Kind == ARMInstrInfo::tk_LDR_PCREL)
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res.SpecialKind = special_LoadLiteral;
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res.EndBlock |= res.Branches();
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@ -377,7 +381,7 @@ Info Decode(bool thumb, u32 num, u32 instr)
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if (data & A_UnkOnARM7 && num != 0)
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data = A_UNK;
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res.Kind = (data >> 21) & 0x1FF;
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res.Kind = (data >> 22) & 0x1FF;
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if (res.Kind == ak_MCR)
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{
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@ -454,12 +458,15 @@ Info Decode(bool thumb, u32 num, u32 instr)
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res.ReadFlags |= flag_C;
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if ((data & A_RRXReadC) && !((instr >> 7) & 0x1F))
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res.ReadFlags |= flag_C;
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if ((data & A_SetC) || (data & A_StaticShiftSetC) && ((instr >> 7) & 0x1F))
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if ((data & A_SetC) || ((data & A_StaticShiftSetC) && ((instr >> 7) & 0x1F)))
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res.WriteFlags |= flag_C;
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if (data & A_WriteMem)
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res.SpecialKind = special_WriteMem;
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if ((data & A_LoadMem) && res.SrcRegs == (1 << 15))
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res.SpecialKind = special_LoadLiteral;
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if ((instr >> 28) < 0xE)
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{
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// make non conditional flag sets conditional
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@ -230,7 +230,8 @@ enum
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{
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special_NotSpecialAtAll = 0,
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special_WriteMem,
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special_WaitForInterrupt
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special_WaitForInterrupt,
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special_LoadLiteral
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};
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struct Info
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