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implement stm

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This commit is contained in:
Jaklyy 2024-06-02 10:33:29 -04:00
parent 63d4b78733
commit b5c1ee33fb
4 changed files with 30 additions and 19 deletions
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6
src/ARM.cpp
View File

@ -1203,21 +1203,23 @@ void ARMv4::DataWrite16(u32 addr, u16 val)
DataCycles = NDS.ARM7MemTimings[addr >> 15][0];
}
void ARMv4::DataWrite32(u32 addr, u32 val)
bool ARMv4::DataWrite32(u32 addr, u32 val)
{
addr &= ~3;
BusWrite32(addr, val);
DataRegion = addr;
DataCycles = NDS.ARM7MemTimings[addr >> 15][2];
return true;
}
void ARMv4::DataWrite32S(u32 addr, u32 val)
bool ARMv4::DataWrite32S(u32 addr, u32 val)
{
addr &= ~3;
BusWrite32(addr, val);
DataCycles += NDS.ARM7MemTimings[addr >> 15][3];
return true;
}

12
src/ARM.h
View File

@ -134,8 +134,8 @@ public:
virtual bool DataRead32S(u32 addr, u32* val) = 0;
virtual void DataWrite8(u32 addr, u8 val) = 0;
virtual void DataWrite16(u32 addr, u16 val) = 0;
virtual void DataWrite32(u32 addr, u32 val) = 0;
virtual void DataWrite32S(u32 addr, u32 val) = 0;
virtual bool DataWrite32(u32 addr, u32 val) = 0;
virtual bool DataWrite32S(u32 addr, u32 val) = 0;
virtual void AddCycles_C() = 0;
virtual void AddCycles_CI(s32 numI) = 0;
@ -255,8 +255,8 @@ public:
bool DataRead32S(u32 addr, u32* val) override;
void DataWrite8(u32 addr, u8 val) override;
void DataWrite16(u32 addr, u16 val) override;
void DataWrite32(u32 addr, u32 val) override;
void DataWrite32S(u32 addr, u32 val) override;
bool DataWrite32(u32 addr, u32 val) override;
bool DataWrite32S(u32 addr, u32 val) override;
void AddCycles_C() override
{
@ -404,8 +404,8 @@ public:
bool DataRead32S(u32 addr, u32* val) override;
void DataWrite8(u32 addr, u8 val) override;
void DataWrite16(u32 addr, u16 val) override;
void DataWrite32(u32 addr, u32 val) override;
void DataWrite32S(u32 addr, u32 val) override;
bool DataWrite32(u32 addr, u32 val) override;
bool DataWrite32S(u32 addr, u32 val) override;
void AddCycles_C() override;
void AddCycles_CI(s32 num) override;
void AddCycles_CDI() override;

9
src/ARMInterpreter_LoadStore.cpp
View File

@ -490,6 +490,7 @@ void A_STM(ARM* cpu)
u32 oldbase = base;
u32 preinc = (cpu->CurInstr & (1<<24));
bool first = true;
bool dataabort = false;
if (!(cpu->CurInstr & (1<<23)))
{
@ -526,12 +527,12 @@ void A_STM(ARM* cpu)
if (i == baseid && !isbanked)
{
if ((cpu->Num == 0) || (!(cpu->CurInstr & ((1<<i)-1))))
first ? cpu->DataWrite32(base, oldbase) : cpu->DataWrite32S(base, oldbase);
{if (!(first ? cpu->DataWrite32(base, oldbase) : cpu->DataWrite32S(base, oldbase))) {dataabort = true; break;}}
else
first ? cpu->DataWrite32(base, base) : cpu->DataWrite32S(base, base); // checkme
if (!(first ? cpu->DataWrite32(base, base) : cpu->DataWrite32S(base, base))) {dataabort = true; break;} // checkme
}
else
first ? cpu->DataWrite32(base, cpu->R[i]) : cpu->DataWrite32S(base, cpu->R[i]);
if (!(first ? cpu->DataWrite32(base, cpu->R[i]) : cpu->DataWrite32S(base, cpu->R[i]))) {dataabort = true; break;}
first = false;
@ -542,7 +543,7 @@ void A_STM(ARM* cpu)
if (cpu->CurInstr & (1<<22))
cpu->UpdateMode((cpu->CPSR&~0x1F)|0x10, cpu->CPSR, true);
if ((cpu->CurInstr & (1<<23)) && (cpu->CurInstr & (1<<21)))
if ((cpu->CurInstr & (1<<23)) && (cpu->CurInstr & (1<<21)) && !dataabort)
cpu->R[baseid] = base;
cpu->AddCycles_CD();

22
src/CP15.cpp
View File

@ -979,12 +979,12 @@ void ARMv5::DataWrite16(u32 addr, u16 val)
DataCycles = MemTimings[addr >> 12][1];
}
void ARMv5::DataWrite32(u32 addr, u32 val)
bool ARMv5::DataWrite32(u32 addr, u32 val)
{
if (!(PU_Map[addr>>12] & 0x02))
{
DataAbort();
return;
return false;
}
DataRegion = addr;
@ -996,21 +996,28 @@ void ARMv5::DataWrite32(u32 addr, u32 val)
DataCycles = 1;
*(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
return;
return true;
}
if ((addr & DTCMMask) == DTCMBase)
{
DataCycles = 1;
*(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return;
return true;
}
BusWrite32(addr, val);
DataCycles = MemTimings[addr >> 12][2];
return true;
}
void ARMv5::DataWrite32S(u32 addr, u32 val)
bool ARMv5::DataWrite32S(u32 addr, u32 val)
{
if (!(PU_Map[addr>>12] & 0x02))
{
DataAbort();
return false;
}
addr &= ~3;
if (addr < ITCMSize)
@ -1020,17 +1027,18 @@ void ARMv5::DataWrite32S(u32 addr, u32 val)
#ifdef JIT_ENABLED
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
#endif
return;
return true;
}
if ((addr & DTCMMask) == DTCMBase)
{
DataCycles += 1;
*(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return;
return true;
}
BusWrite32(addr, val);
DataCycles += MemTimings[addr >> 12][3];
return true;
}
void ARMv5::GetCodeMemRegion(u32 addr, MemRegion* region)