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implement stm

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This commit is contained in:
Jaklyy
2024-06-02 10:33:29 -04:00
parent 63d4b78733
commit b5c1ee33fb
4 changed files with 30 additions and 19 deletions
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22
src/CP15.cpp
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@ -979,12 +979,12 @@ void ARMv5::DataWrite16(u32 addr, u16 val)
DataCycles = MemTimings[addr >> 12][1];
}
void ARMv5::DataWrite32(u32 addr, u32 val)
bool ARMv5::DataWrite32(u32 addr, u32 val)
{
if (!(PU_Map[addr>>12] & 0x02))
{
DataAbort();
return;
return false;
}
DataRegion = addr;
@ -996,21 +996,28 @@ void ARMv5::DataWrite32(u32 addr, u32 val)
DataCycles = 1;
*(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
return;
return true;
}
if ((addr & DTCMMask) == DTCMBase)
{
DataCycles = 1;
*(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return;
return true;
}
BusWrite32(addr, val);
DataCycles = MemTimings[addr >> 12][2];
return true;
}
void ARMv5::DataWrite32S(u32 addr, u32 val)
bool ARMv5::DataWrite32S(u32 addr, u32 val)
{
if (!(PU_Map[addr>>12] & 0x02))
{
DataAbort();
return false;
}
addr &= ~3;
if (addr < ITCMSize)
@ -1020,17 +1027,18 @@ void ARMv5::DataWrite32S(u32 addr, u32 val)
#ifdef JIT_ENABLED
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
#endif
return;
return true;
}
if ((addr & DTCMMask) == DTCMBase)
{
DataCycles += 1;
*(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return;
return true;
}
BusWrite32(addr, val);
DataCycles += MemTimings[addr >> 12][3];
return true;
}
void ARMv5::GetCodeMemRegion(u32 addr, MemRegion* region)