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fix regression from last commit

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also a small mistake with msr
This commit is contained in:
RSDuck 2020-04-26 23:25:32 +02:00
parent b0b9ec42e4
commit bcc4b5c8dd
2 changed files with 17 additions and 9 deletions
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2
src/ARMJIT_x64/ARMJIT_Compiler.cpp
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@ -105,7 +105,7 @@ void Compiler::A_Comp_MSR()
if ((mask & 0xFF) == 0)
{
AND(32, R(RCPSR), Imm32(~mask));
if (val.IsImm())
if (!val.IsImm())
{
MOV(32, R(RSCRATCH), val);
AND(32, R(RSCRATCH), Imm32(mask));

24
src/ARMJIT_x64/ARMJIT_LoadStore.cpp
View File

@ -502,14 +502,6 @@ s32 Compiler::Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc
int regsCount = regs.Count();
if (decrement)
{
MOV_sum(32, ABI_PARAM1, MapReg(rn), Imm32(-regsCount * 4));
preinc ^= true;
}
else
MOV(32, R(ABI_PARAM1), MapReg(rn));
s32 offset = (regsCount * 4) * (decrement ? -1 : 1);
// we need to make sure that the stack stays aligned to 16 bytes
@ -519,6 +511,14 @@ s32 Compiler::Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc
{
Comp_AddCycles_CDI();
if (decrement)
{
MOV_sum(32, ABI_PARAM1, MapReg(rn), Imm32(-regsCount * 4));
preinc ^= true;
}
else
MOV(32, R(ABI_PARAM1), MapReg(rn));
MOV(32, R(ABI_PARAM3), Imm32(regsCount));
SUB(64, R(RSP), stackAlloc <= INT8_MAX ? Imm8(stackAlloc) : Imm32(stackAlloc));
MOV(64, R(ABI_PARAM2), R(RSP));
@ -618,6 +618,14 @@ s32 Compiler::Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc
}
}
if (decrement)
{
MOV_sum(32, ABI_PARAM1, MapReg(rn), Imm32(-regsCount * 4));
preinc ^= true;
}
else
MOV(32, R(ABI_PARAM1), MapReg(rn));
MOV(64, R(ABI_PARAM2), R(RSP));
MOV(32, R(ABI_PARAM3), Imm32(regsCount));