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synced 2024-11-14 13:27:41 -07:00
unaligned registers with strd/ldrd raise an exception
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@ -251,7 +251,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
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if (cpu->Num != 0) return; \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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u32 r = (cpu->CurInstr>>12) & 0xF; \
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if (r&1) { r--; printf("!! MISALIGNED LDRD %d\n", r+1); } \
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if (r&1) { A_UNK(cpu); return; } \
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if (!cpu->DataRead32 (offset , &cpu->R[r ])) {cpu->AddCycles_CDI(); return;} \
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if (!cpu->DataRead32S(offset+4, &cpu->R[r+1])) {cpu->AddCycles_CDI(); return;} \
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cpu->AddCycles_CDI(); \
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@ -261,7 +261,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
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if (cpu->Num != 0) return; \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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u32 r = (cpu->CurInstr>>12) & 0xF; \
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if (r&1) { r--; printf("!! MISALIGNED LDRD_POST %d\n", r+1); } \
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if (r&1) { A_UNK(cpu); return; } \
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if (!cpu->DataRead32 (addr , &cpu->R[r ])) {cpu->AddCycles_CDI(); return;} \
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if (!cpu->DataRead32S(addr+4, &cpu->R[r+1])) {cpu->AddCycles_CDI(); return;} \
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cpu->AddCycles_CDI(); \
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@ -271,7 +271,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
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if (cpu->Num != 0) return; \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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u32 r = (cpu->CurInstr>>12) & 0xF; \
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if (r&1) { r--; printf("!! MISALIGNED STRD %d\n", r+1); } \
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if (r&1) { A_UNK(cpu); return; } \
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bool dataabort = !cpu->DataWrite32(offset, cpu->R[r ]); /* yes, this data abort behavior is on purpose */ \
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dataabort |= !cpu->DataWrite32S (offset+4, cpu->R[r+1], dataabort); /* no, i dont understand it either */ \
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cpu->AddCycles_CD(); \
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@ -282,7 +282,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
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if (cpu->Num != 0) return; \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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u32 r = (cpu->CurInstr>>12) & 0xF; \
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if (r&1) { r--; printf("!! MISALIGNED STRD_POST %d\n", r+1); } \
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if (r&1) { A_UNK(cpu); return; } \
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bool dataabort = !cpu->DataWrite32(addr, cpu->R[r ]); \
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dataabort |= !cpu->DataWrite32S (addr+4, cpu->R[r+1], dataabort); \
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cpu->AddCycles_CD(); \
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