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https://github.com/melonDS-emu/melonDS.git
synced 2024-11-14 13:27:41 -07:00
fix bug that could cause nested IRQs.
fix potential bug in MSR.
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parent
7f5ee5c00e
commit
bff3a92cc0
15
ARM.cpp
15
ARM.cpp
@ -210,18 +210,9 @@ void ARM::UpdateMode(u32 oldmode, u32 newmode)
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void ARM::TriggerIRQ()
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{
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if ((CPSR & 0x80) && (!Halted))
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if (CPSR & 0x80)
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return;
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/*if (Num==1)
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{
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printf("ARM7 IRQ %08X %08X\n", R[15], R_IRQ[0]);
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if (NDS::Timers[5].Event)
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{
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printf("Timer1 %d %d\n", NDS::Timers[5].Counter, NDS::Timers[5].Event->Delay);
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}
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}*/
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u32 oldcpsr = CPSR;
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CPSR &= ~0xFF;
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CPSR |= 0xD2;
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@ -298,9 +289,7 @@ s32 ARM::Execute(s32 cycles)
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TriggerIRQ();
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}
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//if (R[15] >= 0x3800170+4 && R[15]<=0x0380017A+4)
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// printf("!! %08X: %08X | %08X %08X\n", R[15]-4, R[13], R[0], R[1]);
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// temp. debug cruft
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addr = R[15] - (CPSR&0x20 ? 4:8);
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cpsr = CPSR;
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}
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@ -67,11 +67,14 @@ s32 A_MSR_IMM(ARM* cpu)
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u32 oldpsr = *psr;
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u32 mask = 0;
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if (cpu->CurInstr & (1<<16)) mask |= 0x000000DF;
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if (cpu->CurInstr & (1<<16)) mask |= 0x000000FF;
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if (cpu->CurInstr & (1<<17)) mask |= 0x0000FF00;
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if (cpu->CurInstr & (1<<18)) mask |= 0x00FF0000;
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if (cpu->CurInstr & (1<<19)) mask |= 0xFF000000;
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if (!(cpu->CurInstr & (1<<22)))
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mask &= 0xFFFFFFDF;
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if ((cpu->CPSR & 0x1F) == 0x10) mask &= 0xFFFFFF00;
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u32 val = ROR((cpu->CurInstr & 0xFF), ((cpu->CurInstr >> 7) & 0x1E));
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@ -10,7 +10,7 @@
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1481161027 c:\documents\sources\melonds\types.h
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1484699425 source:c:\documents\sources\melonds\nds.cpp
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1484702383 source:c:\documents\sources\melonds\nds.cpp
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<stdio.h>
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<string.h>
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"NDS.h"
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@ -22,7 +22,7 @@
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"SPI.h"
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"Wifi.h"
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1484699468 source:c:\documents\sources\melonds\arm.cpp
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1484705354 source:c:\documents\sources\melonds\arm.cpp
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<stdio.h>
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"NDS.h"
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"ARM.h"
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@ -38,7 +38,7 @@
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"types.h"
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"ARM.h"
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1484538181 source:c:\documents\sources\melonds\arminterpreter.cpp
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1484704018 source:c:\documents\sources\melonds\arminterpreter.cpp
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<stdio.h>
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"NDS.h"
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"CP15.h"
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