mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-24 14:49:53 -06:00
jit: thumb block transfer working
also pc and sp relative loads and some refactoring
This commit is contained in:
RSDuck
@ -3,16 +3,6 @@
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#include "../GPU.h"
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#include "../Wifi.h"
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namespace NDS
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{
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extern u8* SWRAM_ARM9;
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extern u32 SWRAM_ARM9Mask;
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extern u8* SWRAM_ARM7;
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extern u32 SWRAM_ARM7Mask;
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extern u8 ARM7WRAM[];
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extern u16 ARM7BIOSProt;
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}
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using namespace Gen;
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namespace ARMJIT
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@ -41,6 +31,49 @@ int squeezePointer(T* ptr)
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store value - ABI_PARAM2 (a.k.a. RDX = RSCRATCH2 on Windows)
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code cycles - ABI_PARAM3
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*/
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#define CALC_CYCLES_9(numC, numD, scratch) \
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LEA(32, scratch, MComplex(numD, numC, SCALE_1, -6)); \
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CMP(32, R(numC), R(numD)); \
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CMOVcc(32, numD, R(numC), CC_G); \
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CMP(32, R(numD), R(scratch)); \
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CMOVcc(32, scratch, R(numD), CC_G); \
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ADD(32, MDisp(RCPU, offsetof(ARM, Cycles)), R(scratch));
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#define CALC_CYCLES_7_DATA_MAIN_RAM(numC, numD, scratch) \
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if (codeMainRAM) \
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{ \
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LEA(32, scratch, MRegSum(numD, numC)); \
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ADD(32, MDisp(RCPU, offsetof(ARM, Cycles)), R(scratch)); \
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} \
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else \
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{ \
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if (!store) \
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ADD(32, R(numC), Imm8(1)); \
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LEA(32, scratch, MComplex(numD, numC, SCALE_1, -3)); \
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CMP(32, R(numD), R(numC)); \
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CMOVcc(32, numC, R(numD), CC_G); \
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CMP(32, R(numC), R(scratch)); \
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CMOVcc(32, scratch, R(numC), CC_G); \
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ADD(32, MDisp(RCPU, offsetof(ARM, Cycles)), R(scratch)); \
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}
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#define CALC_CYCLES_7_DATA_NON_MAIN_RAM(numC, numD, scratch) \
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if (codeMainRAM) \
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{ \
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if (!store) \
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ADD(32, R(numD), Imm8(1)); \
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LEA(32, scratch, MComplex(numD, numC, SCALE_1, -3)); \
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CMP(32, R(numD), R(numC)); \
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CMOVcc(32, numC, R(numD), CC_G); \
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CMP(32, R(numC), R(scratch)); \
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CMOVcc(32, scratch, R(numC), CC_G); \
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ADD(32, MDisp(RCPU, offsetof(ARM, Cycles)), R(scratch)); \
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} \
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else \
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{ \
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LEA(32, scratch, MComplex(numD, numC, SCALE_1, store ? 0 : 1)); \
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ADD(32, MDisp(RCPU, offsetof(ARM, Cycles)), R(scratch)); \
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}
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void* Compiler::Gen_MemoryRoutine9(bool store, int size)
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{
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u32 addressMask = ~(size == 32 ? 3 : (size == 16 ? 1 : 0));
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@ -56,15 +89,10 @@ void* Compiler::Gen_MemoryRoutine9(bool store, int size)
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FixupBranch insideITCM = J_CC(CC_B);
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// cycle counting!
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MOV(32, R(RSCRATCH), R(ABI_PARAM1));
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SHR(32, R(RSCRATCH), Imm8(12));
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MOVZX(32, 8, RSCRATCH, MComplex(RCPU, RSCRATCH, SCALE_1, offsetof(ARMv5, MemTimings) + (size == 32 ? 2 : 0)));
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LEA(32, ABI_PARAM4, MComplex(RSCRATCH, ABI_PARAM3, SCALE_1, -6));
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CMP(32, R(ABI_PARAM3), R(RSCRATCH));
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CMOVcc(32, RSCRATCH, R(ABI_PARAM3), CC_G);
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CMP(32, R(ABI_PARAM4), R(RSCRATCH));
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CMOVcc(32, RSCRATCH, R(ABI_PARAM4), CC_G);
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ADD(32, R(RCycles), R(RSCRATCH));
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MOV(32, R(ABI_PARAM4), R(ABI_PARAM1));
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SHR(32, R(ABI_PARAM4), Imm8(12));
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MOVZX(32, 8, ABI_PARAM4, MComplex(RCPU, ABI_PARAM4, SCALE_4, offsetof(ARMv5, MemTimings) + (size == 32 ? 2 : 1)));
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CALC_CYCLES_9(ABI_PARAM3, ABI_PARAM4, RSCRATCH)
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if (store)
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{
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@ -101,7 +129,7 @@ void* Compiler::Gen_MemoryRoutine9(bool store, int size)
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}
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SetJumpTarget(insideDTCM);
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ADD(32, R(RCycles), R(ABI_PARAM3));
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ADD(32, MDisp(RCPU, offsetof(ARM, Cycles)), R(ABI_PARAM3));
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AND(32, R(RSCRATCH), Imm32(0x3FFF & addressMask));
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if (store)
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MOV(size, MComplex(RCPU, RSCRATCH, SCALE_1, offsetof(ARMv5, DTCM)), R(ABI_PARAM2));
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@ -120,7 +148,7 @@ void* Compiler::Gen_MemoryRoutine9(bool store, int size)
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RET();
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SetJumpTarget(insideITCM);
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ADD(32, R(RCycles), R(ABI_PARAM3));
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ADD(32, MDisp(RCPU, offsetof(ARM, Cycles)), R(ABI_PARAM3));
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MOV(32, R(ABI_PARAM3), R(ABI_PARAM1)); // free up ECX
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AND(32, R(ABI_PARAM3), Imm32(0x7FFF & addressMask));
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if (store)
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@ -158,28 +186,13 @@ void* Compiler::Gen_MemoryRoutine7(bool store, bool codeMainRAM, int size)
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MOV(32, R(RSCRATCH), R(ABI_PARAM1));
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SHR(32, R(RSCRATCH), Imm8(15));
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MOVZX(32, 8, ABI_PARAM4, MDisp(RSCRATCH, (size == 32 ? 2 : 0) + squeezePointer(NDS::ARM7MemTimings)));
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MOVZX(32, 8, ABI_PARAM4, MScaled(RSCRATCH, SCALE_4, (size == 32 ? 2 : 0) + squeezePointer(NDS::ARM7MemTimings)));
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MOV(32, R(RSCRATCH), R(ABI_PARAM1));
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AND(32, R(RSCRATCH), Imm32(0xFF000000));
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CMP(32, R(RSCRATCH), Imm32(0x02000000));
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FixupBranch outsideMainRAM = J_CC(CC_NE);
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if (codeMainRAM)
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{
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LEA(32, RSCRATCH, MRegSum(ABI_PARAM4, ABI_PARAM3));
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ADD(32, R(RCycles), R(RSCRATCH));
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}
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else
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{
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if (!store)
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ADD(32, R(ABI_PARAM3), Imm8(1));
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LEA(32, RSCRATCH, MComplex(ABI_PARAM4, ABI_PARAM3, SCALE_1, -3));
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CMP(32, R(ABI_PARAM4), R(ABI_PARAM3));
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CMOVcc(32, ABI_PARAM3, R(ABI_PARAM4), CC_G);
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CMP(32, R(ABI_PARAM3), R(RSCRATCH));
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CMOVcc(32, RSCRATCH, R(ABI_PARAM3), CC_G);
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ADD(32, R(RCycles), R(RSCRATCH));
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}
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CALC_CYCLES_7_DATA_MAIN_RAM(ABI_PARAM3, ABI_PARAM4, RSCRATCH)
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MOV(32, R(ABI_PARAM3), R(ABI_PARAM1));
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AND(32, R(ABI_PARAM3), Imm32((MAIN_RAM_SIZE - 1) & addressMask));
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if (store)
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@ -205,22 +218,7 @@ void* Compiler::Gen_MemoryRoutine7(bool store, bool codeMainRAM, int size)
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RET();
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SetJumpTarget(outsideMainRAM);
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if (codeMainRAM)
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{
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if (!store)
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ADD(32, R(ABI_PARAM4), Imm8(1));
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LEA(32, RSCRATCH, MComplex(ABI_PARAM4, ABI_PARAM3, SCALE_1, -3));
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CMP(32, R(ABI_PARAM4), R(ABI_PARAM3));
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CMOVcc(32, ABI_PARAM3, R(ABI_PARAM4), CC_G);
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CMP(32, R(ABI_PARAM3), R(RSCRATCH));
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CMOVcc(32, RSCRATCH, R(ABI_PARAM3), CC_G);
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ADD(32, R(RCycles), R(RSCRATCH));
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}
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else
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{
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LEA(32, RSCRATCH, MComplex(ABI_PARAM4, ABI_PARAM3, SCALE_1, store ? 0 : 1));
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ADD(32, R(RCycles), R(RSCRATCH));
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}
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CALC_CYCLES_7_DATA_NON_MAIN_RAM(ABI_PARAM3, ABI_PARAM4, RSCRATCH)
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if (store)
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{
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if (size > 8)
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@ -257,7 +255,189 @@ void* Compiler::Gen_MemoryRoutine7(bool store, bool codeMainRAM, int size)
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return res;
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}
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void Compiler::Comp_MemAccess(Gen::OpArg rd, bool signExtend, bool store, int size)
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#define MEMORY_SEQ_WHILE_COND \
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if (!store) \
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MOV(32, currentElement, R(EAX));\
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if (!preinc) \
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ADD(32, R(ABI_PARAM1), Imm8(4)); \
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\
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SUB(32, R(ABI_PARAM3), Imm8(1)); \
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J_CC(CC_NZ, repeat);
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/*
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ABI_PARAM1 address
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ABI_PARAM2 address where registers are stored
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ABI_PARAM3 how many values to read/write
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ABI_PARAM4 code cycles
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Dolphin x64CodeEmitter is my favourite assembler
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*/
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void* Compiler::Gen_MemoryRoutineSeq9(bool store, bool preinc)
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{
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const u8* zero = GetCodePtr();
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ADD(32, MDisp(RCPU, offsetof(ARM, Cycles)), R(ABI_PARAM4));
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RET();
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void* res = (void*)GetWritableCodePtr();
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TEST(32, R(ABI_PARAM3), R(ABI_PARAM3));
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J_CC(CC_Z, zero);
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PUSH(ABI_PARAM3);
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PUSH(ABI_PARAM4); // we need you later
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const u8* repeat = GetCodePtr();
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if (preinc)
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ADD(32, R(ABI_PARAM1), Imm8(4));
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MOV(32, R(RSCRATCH), R(ABI_PARAM1));
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SUB(32, R(RSCRATCH), MDisp(RCPU, offsetof(ARMv5, DTCMBase)));
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CMP(32, R(RSCRATCH), MDisp(RCPU, offsetof(ARMv5, DTCMSize)));
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FixupBranch insideDTCM = J_CC(CC_B);
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CMP(32, R(ABI_PARAM1), MDisp(RCPU, offsetof(ARMv5, ITCMSize)));
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FixupBranch insideITCM = J_CC(CC_B);
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OpArg currentElement = MComplex(ABI_PARAM2, ABI_PARAM3, SCALE_8, -8); // wasting stack space like a gangster
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ABI_PushRegistersAndAdjustStack({ABI_PARAM1, ABI_PARAM2, ABI_PARAM3}, 8);
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AND(32, R(ABI_PARAM1), Imm8(~3));
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if (store)
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{
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MOV(32, R(ABI_PARAM2), currentElement);
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CALL((void*)NDS::ARM9Write32);
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}
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else
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CALL((void*)NDS::ARM9Read32);
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ABI_PopRegistersAndAdjustStack({ABI_PARAM1, ABI_PARAM2, ABI_PARAM3}, 8);
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MEMORY_SEQ_WHILE_COND
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MOV(32, R(RSCRATCH), R(ABI_PARAM1));
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SHR(32, R(RSCRATCH), Imm8(12));
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MOVZX(32, 8, ABI_PARAM2, MComplex(RCPU, RSCRATCH, SCALE_4, 2 + offsetof(ARMv5, MemTimings)));
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MOVZX(32, 8, RSCRATCH, MComplex(RCPU, RSCRATCH, SCALE_4, 3 + offsetof(ARMv5, MemTimings)));
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FixupBranch finishIt1 = J();
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SetJumpTarget(insideDTCM);
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AND(32, R(RSCRATCH), Imm32(0x3FFF & ~3));
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if (store)
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{
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MOV(32, R(ABI_PARAM4), currentElement);
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MOV(32, MComplex(RCPU, RSCRATCH, SCALE_1, offsetof(ARMv5, DTCM)), R(ABI_PARAM4));
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}
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else
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MOV(32, R(RSCRATCH), MComplex(RCPU, RSCRATCH, SCALE_1, offsetof(ARMv5, DTCM)));
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MEMORY_SEQ_WHILE_COND
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MOV(32, R(RSCRATCH), Imm32(1)); // sequential access time
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MOV(32, R(ABI_PARAM2), Imm32(1)); // non sequential
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FixupBranch finishIt2 = J();
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SetJumpTarget(insideITCM);
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MOV(32, R(RSCRATCH), R(ABI_PARAM1));
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AND(32, R(RSCRATCH), Imm32(0x7FFF & ~3));
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if (store)
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{
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MOV(32, R(ABI_PARAM4), currentElement);
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MOV(32, MComplex(RCPU, RSCRATCH, SCALE_1, offsetof(ARMv5, ITCM)), R(ABI_PARAM4));
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XOR(32, R(ABI_PARAM4), R(ABI_PARAM4));
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MOV(64, MScaled(RSCRATCH, SCALE_4, squeezePointer(cache.ARM9_ITCM)), R(ABI_PARAM4));
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MOV(64, MScaled(RSCRATCH, SCALE_4, squeezePointer(cache.ARM9_ITCM) + 8), R(ABI_PARAM4));
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}
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else
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MOV(32, R(RSCRATCH), MComplex(RCPU, RSCRATCH, SCALE_1, offsetof(ARMv5, ITCM)));
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MEMORY_SEQ_WHILE_COND
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MOV(32, R(RSCRATCH), Imm32(1));
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MOV(32, R(ABI_PARAM2), Imm32(1));
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SetJumpTarget(finishIt1);
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SetJumpTarget(finishIt2);
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POP(ABI_PARAM4);
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POP(ABI_PARAM3);
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CMP(32, R(ABI_PARAM3), Imm8(1));
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FixupBranch skipSequential = J_CC(CC_E);
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SUB(32, R(ABI_PARAM3), Imm8(1));
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IMUL(32, R(ABI_PARAM3));
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ADD(32, R(ABI_PARAM2), R(RSCRATCH));
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SetJumpTarget(skipSequential);
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CALC_CYCLES_9(ABI_PARAM4, ABI_PARAM2, RSCRATCH)
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RET();
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return res;
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}
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void* Compiler::Gen_MemoryRoutineSeq7(bool store, bool preinc, bool codeMainRAM)
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{
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const u8* zero = GetCodePtr();
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ADD(32, MDisp(RCPU, offsetof(ARM, Cycles)), R(ABI_PARAM4));
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RET();
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void* res = (void*)GetWritableCodePtr();
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TEST(32, R(ABI_PARAM3), R(ABI_PARAM3));
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J_CC(CC_Z, zero);
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PUSH(ABI_PARAM3);
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PUSH(ABI_PARAM4); // we need you later
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const u8* repeat = GetCodePtr();
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if (preinc)
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ADD(32, R(ABI_PARAM1), Imm8(4));
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OpArg currentElement = MComplex(ABI_PARAM2, ABI_PARAM3, SCALE_8, -8);
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ABI_PushRegistersAndAdjustStack({ABI_PARAM1, ABI_PARAM2, ABI_PARAM3}, 8);
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AND(32, R(ABI_PARAM1), Imm8(~3));
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if (store)
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{
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MOV(32, R(ABI_PARAM2), currentElement);
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CALL((void*)NDS::ARM7Write32);
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}
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else
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CALL((void*)NDS::ARM7Read32);
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ABI_PopRegistersAndAdjustStack({ABI_PARAM1, ABI_PARAM2, ABI_PARAM3}, 8);
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MEMORY_SEQ_WHILE_COND
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MOV(32, R(RSCRATCH), R(ABI_PARAM1));
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SHR(32, R(RSCRATCH), Imm8(15));
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MOVZX(32, 8, ABI_PARAM2, MScaled(RSCRATCH, SCALE_4, 2 + squeezePointer(NDS::ARM7MemTimings)));
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MOVZX(32, 8, RSCRATCH, MScaled(RSCRATCH, SCALE_4, 3 + squeezePointer(NDS::ARM7MemTimings)));
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POP(ABI_PARAM4);
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POP(ABI_PARAM3);
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CMP(32, R(ABI_PARAM3), Imm8(1));
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FixupBranch skipSequential = J_CC(CC_E);
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SUB(32, R(ABI_PARAM3), Imm8(1));
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IMUL(32, R(ABI_PARAM3));
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ADD(32, R(ABI_PARAM2), R(RSCRATCH));
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SetJumpTarget(skipSequential);
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MOV(32, R(RSCRATCH), R(ABI_PARAM1));
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AND(32, R(RSCRATCH), Imm32(0xFF000000));
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CMP(32, R(RSCRATCH), Imm32(0x02000000));
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FixupBranch outsideMainRAM = J_CC(CC_NE);
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CALC_CYCLES_7_DATA_MAIN_RAM(ABI_PARAM4, ABI_PARAM2, RSCRATCH)
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RET();
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SetJumpTarget(outsideMainRAM);
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CALC_CYCLES_7_DATA_NON_MAIN_RAM(ABI_PARAM4, ABI_PARAM2, RSCRATCH)
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RET();
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return res;
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}
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#undef CALC_CYCLES_9
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#undef MEMORY_SEQ_WHILE_COND
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void Compiler::Comp_MemAccess(OpArg rd, bool signExtend, bool store, int size)
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{
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if (store)
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MOV(32, R(ABI_PARAM2), rd);
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@ -278,6 +458,129 @@ void Compiler::Comp_MemAccess(Gen::OpArg rd, bool signExtend, bool store, int si
|
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}
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}
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s32 Compiler::Comp_MemAccessBlock(OpArg rb, BitSet16 regs, bool store, bool preinc, bool decrement, bool usermode)
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{
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int regsCount = regs.Count();
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const u8 userModeOffsets[] =
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{
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offsetof(ARM, R[8]), offsetof(ARM, R[9]), offsetof(ARM, R[10]), offsetof(ARM, R[11]),
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offsetof(ARM, R[12]), offsetof(ARM, R[13]), offsetof(ARM, R[14]), 0,
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offsetof(ARM, R_FIQ[0]), offsetof(ARM, R_FIQ[1]), offsetof(ARM, R_FIQ[2]), offsetof(ARM, R_FIQ[3]),
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offsetof(ARM, R_FIQ[4]), offsetof(ARM, R_FIQ[5]), offsetof(ARM, R_FIQ[6]), 0,
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offsetof(ARM, R[8]), offsetof(ARM, R[9]), offsetof(ARM, R[10]), offsetof(ARM, R[11]),
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offsetof(ARM, R[12]), offsetof(ARM, R_IRQ[13]), offsetof(ARM, R_IRQ[14]), 0,
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offsetof(ARM, R[8]), offsetof(ARM, R[9]), offsetof(ARM, R[10]), offsetof(ARM, R[11]),
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offsetof(ARM, R[12]), offsetof(ARM, R_SVC[13]), offsetof(ARM, R_SVC[14]), 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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|
||||
offsetof(ARM, R[8]), offsetof(ARM, R[9]), offsetof(ARM, R[10]), offsetof(ARM, R[11]),
|
||||
offsetof(ARM, R[12]), offsetof(ARM, R_ABT[13]), offsetof(ARM, R_ABT[14]), 0,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
offsetof(ARM, R[8]), offsetof(ARM, R[9]), offsetof(ARM, R[10]), offsetof(ARM, R[11]),
|
||||
offsetof(ARM, R[12]), offsetof(ARM, R_UND[13]), offsetof(ARM, R_UND[14]), 0,
|
||||
};
|
||||
|
||||
if (decrement)
|
||||
{
|
||||
MOV_sum(32, ABI_PARAM1, rb, Imm32(-regsCount * 4));
|
||||
preinc = !preinc;
|
||||
}
|
||||
else
|
||||
MOV(32, R(ABI_PARAM1), rb);
|
||||
|
||||
MOV(32, R(ABI_PARAM3), Imm32(regsCount));
|
||||
u32 cycles = Num
|
||||
? NDS::ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 0 : 2]
|
||||
: (R15 & 0x2 ? 0 : CurInstr.CodeCycles);
|
||||
MOV(32, R(ABI_PARAM4), Imm32(cycles));
|
||||
if (!store)
|
||||
{
|
||||
SUB(32, R(RSP), regsCount < 16 ? Imm8(regsCount * 8) : Imm32(regsCount * 8));
|
||||
MOV(64, R(ABI_PARAM2), R(RSP));
|
||||
|
||||
CALL(Num == 0
|
||||
? MemoryFuncsSeq9[0][preinc]
|
||||
: MemoryFuncsSeq7[0][preinc][CodeRegion == 0x02]);
|
||||
|
||||
for (int reg = 15; reg >= 0; reg--)
|
||||
{
|
||||
if (regs[reg])
|
||||
{
|
||||
if (usermode && reg >= 8 && reg < 15)
|
||||
{
|
||||
MOV(32, R(RSCRATCH2), R(RCPSR));
|
||||
AND(32, R(RSCRATCH2), Imm8(0x1F));
|
||||
// (RSCRATCH2 - 0x11) * 8 + squeezePointer(userModeOffsets) + (reg - 8), algebra is great!
|
||||
MOVZX(32, 8, RSCRATCH2, MScaled(RSCRATCH2, SCALE_8, squeezePointer(userModeOffsets) - 0x11 * 8 + (reg - 8)));
|
||||
POP(RSCRATCH);
|
||||
MOV(32, MRegSum(RCPU, RSCRATCH2), R(RSCRATCH));
|
||||
}
|
||||
else if (RegCache.Mapping[reg] == INVALID_REG)
|
||||
{
|
||||
assert(reg != 15);
|
||||
|
||||
POP(RSCRATCH);
|
||||
SaveReg(reg, RSCRATCH);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (reg != 15)
|
||||
RegCache.DirtyRegs |= (1 << reg);
|
||||
POP(MapReg(reg).GetSimpleReg());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (regs[15])
|
||||
{
|
||||
if (Num == 1)
|
||||
OR(32, MapReg(15), Imm8(1));
|
||||
Comp_JumpTo(MapReg(15).GetSimpleReg(), usermode);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
for (int reg : regs)
|
||||
{
|
||||
if (usermode && reg >= 8 && reg < 15)
|
||||
{
|
||||
MOV(32, R(RSCRATCH), R(RCPSR));
|
||||
AND(32, R(RSCRATCH), Imm8(0x1F));
|
||||
// (RSCRATCH2 - 0x11) * 8 + squeezePointer(userModeOffsets) + (reg - 8), algebra is great!
|
||||
MOVZX(32, 8, RSCRATCH, MScaled(RSCRATCH, SCALE_8, squeezePointer(userModeOffsets) - 0x11 * 8 + (reg - 8)));
|
||||
MOV(32, R(RSCRATCH), MRegSum(RCPU, RSCRATCH));
|
||||
PUSH(RSCRATCH);
|
||||
}
|
||||
else if (RegCache.Mapping[reg] == INVALID_REG)
|
||||
{
|
||||
LoadReg(reg, RSCRATCH);
|
||||
PUSH(RSCRATCH);
|
||||
}
|
||||
else
|
||||
PUSH(MapReg(reg).GetSimpleReg());
|
||||
}
|
||||
MOV(64, R(ABI_PARAM2), R(RSP));
|
||||
|
||||
CALL(Num == 0
|
||||
? MemoryFuncsSeq9[1][preinc]
|
||||
: MemoryFuncsSeq7[1][preinc][CodeRegion == 0x02]);
|
||||
|
||||
ADD(32, R(RSP), regsCount < 16 ? Imm8(regsCount * 8) : Imm32(regsCount * 8));
|
||||
}
|
||||
|
||||
return (regsCount * 4) * (decrement ? -1 : 1);
|
||||
}
|
||||
|
||||
OpArg Compiler::A_Comp_GetMemWBOffset()
|
||||
{
|
||||
if (!(CurInstr.Instr & (1 << 25)))
|
||||
@ -354,6 +657,25 @@ void Compiler::A_Comp_MemHalf()
|
||||
? Imm32(CurInstr.Instr & 0xF | ((CurInstr.Instr >> 4) & 0xF0))
|
||||
: MapReg(CurInstr.A_Reg(0));
|
||||
|
||||
int op = (CurInstr.Instr >> 5) & 0x3;
|
||||
bool load = CurInstr.Instr & (1 << 20);
|
||||
|
||||
bool signExtend = false;
|
||||
int size;
|
||||
if (!load)
|
||||
{
|
||||
size = op == 1 ? 16 : 32;
|
||||
load = op == 2;
|
||||
}
|
||||
else if (load)
|
||||
{
|
||||
size = op == 2 ? 8 : 16;
|
||||
signExtend = op > 1;
|
||||
}
|
||||
|
||||
if (size == 32 && Num == 1)
|
||||
return; // NOP
|
||||
|
||||
if (CurInstr.Instr & (1 << 24))
|
||||
{
|
||||
if (CurInstr.Instr & (1 << 23))
|
||||
@ -370,19 +692,6 @@ void Compiler::A_Comp_MemHalf()
|
||||
else
|
||||
MOV(32, R(ABI_PARAM1), rn);
|
||||
|
||||
int op = (CurInstr.Instr >> 5) & 0x3;
|
||||
bool load = CurInstr.Instr & (1 << 20);
|
||||
|
||||
bool signExtend = false;
|
||||
int size;
|
||||
if (!load && op == 1)
|
||||
size = 16;
|
||||
else if (load)
|
||||
{
|
||||
size = op == 2 ? 8 : 16;
|
||||
signExtend = op > 1;
|
||||
}
|
||||
|
||||
if (!(CurInstr.Instr & (1 << 24)))
|
||||
{
|
||||
if (CurInstr.Instr & (1 << 23))
|
||||
@ -412,6 +721,24 @@ void Compiler::T_Comp_MemReg()
|
||||
Comp_MemAccess(rd, false, !load, byte ? 8 : 32);
|
||||
}
|
||||
|
||||
void Compiler::A_Comp_LDM_STM()
|
||||
{
|
||||
BitSet16 regs(CurInstr.Instr & 0xFFFF);
|
||||
|
||||
bool load = (CurInstr.Instr >> 20) & 1;
|
||||
bool pre = (CurInstr.Instr >> 24) & 1;
|
||||
bool add = (CurInstr.Instr >> 23) & 1;
|
||||
bool writeback = (CurInstr.Instr >> 21) & 1;
|
||||
bool usermode = (CurInstr.Instr >> 22) & 1;
|
||||
|
||||
OpArg rn = MapReg(CurInstr.A_Reg(16));
|
||||
|
||||
s32 offset = Comp_MemAccessBlock(rn, regs, !load, pre, !add, false);
|
||||
|
||||
if (writeback)
|
||||
ADD(32, rn, offset >= INT8_MIN && offset < INT8_MAX ? Imm8(offset) : Imm32(offset));
|
||||
}
|
||||
|
||||
void Compiler::T_Comp_MemImm()
|
||||
{
|
||||
OpArg rd = MapReg(CurInstr.T_Reg(0));
|
||||
@ -456,4 +783,56 @@ void Compiler::T_Comp_MemImmHalf()
|
||||
Comp_MemAccess(rd, false, !load, 16);
|
||||
}
|
||||
|
||||
void Compiler::T_Comp_LoadPCRel()
|
||||
{
|
||||
OpArg rd = MapReg(CurInstr.T_Reg(8));
|
||||
u32 addr = (R15 & ~0x2) + ((CurInstr.Instr & 0xFF) << 2);
|
||||
|
||||
// hopefully this doesn't break
|
||||
u32 val; CurCPU->DataRead32(addr, &val);
|
||||
MOV(32, rd, Imm32(val));
|
||||
}
|
||||
|
||||
void Compiler::T_Comp_MemSPRel()
|
||||
{
|
||||
u32 offset = (CurInstr.Instr & 0xFF) * 4;
|
||||
OpArg rd = MapReg(CurInstr.T_Reg(8));
|
||||
bool load = CurInstr.Instr & (1 << 11);
|
||||
|
||||
LEA(32, ABI_PARAM1, MDisp(MapReg(13).GetSimpleReg(), offset));
|
||||
|
||||
Comp_MemAccess(rd, false, !load, 32);
|
||||
}
|
||||
|
||||
void Compiler::T_Comp_PUSH_POP()
|
||||
{
|
||||
bool load = CurInstr.Instr & (1 << 11);
|
||||
BitSet16 regs(CurInstr.Instr & 0xFF);
|
||||
if (CurInstr.Instr & (1 << 8))
|
||||
{
|
||||
if (load)
|
||||
regs[15] = true;
|
||||
else
|
||||
regs[14] = true;
|
||||
}
|
||||
|
||||
OpArg sp = MapReg(13);
|
||||
|
||||
s32 offset = Comp_MemAccessBlock(sp, regs, !load, !load, !load, false);
|
||||
|
||||
ADD(32, sp, Imm8(offset)); // offset will be always be in range since PUSH accesses 9 regs max
|
||||
}
|
||||
|
||||
void Compiler::T_Comp_LDMIA_STMIA()
|
||||
{
|
||||
BitSet16 regs(CurInstr.Instr & 0xFF);
|
||||
OpArg rb = MapReg(CurInstr.T_Reg(8));
|
||||
bool load = CurInstr.Instr & (1 << 11);
|
||||
|
||||
s32 offset = Comp_MemAccessBlock(rb, regs, !load, false, false, false);
|
||||
|
||||
if (!load || !regs[CurInstr.T_Reg(8)])
|
||||
ADD(32, rb, Imm8(offset));
|
||||
}
|
||||
|
||||
}
|
||||
Reference in New Issue
Block a user