Commit Graph

18 Commits

Author SHA1 Message Date
052ff73672 rewrite JIT memory emulation 2020-06-16 12:01:08 +02:00
c2dd6a186d implement msr and mrs for the x64 JIT 2020-06-16 11:59:07 +02:00
99b34efe2d move ARM64 JIT backend here 2020-06-16 11:57:51 +02:00
ec965c6014 improve nop handling and proper behaviour for LDM^
fixes dslinux
2020-06-16 11:57:49 +02:00
441869a105 integrate changes from ARM64 backend and more
- better handle LDM/STM in reg alloc
- unify Halted and IRQ in anticipation for branch inlining
- literal optimisations can be disabled in gui
- jit blocks follow simple returns
- fix idle loop detection
- break jit blocks on IRQ (fixes saving in Pokemon White)
2020-06-16 11:57:45 +02:00
9cf7780e46 decrease jit block cache address granularity
fixes Dragon Quest IX
move code with side effects out of assert, fixes release build
(thanks to m4wx for this one)
also remove some leftovers of jit pipelining
2020-06-16 11:56:45 +02:00
40b88ab05a new block cache and much more...
- more reliable code invalidation detection
- blocks aren't stopped at any branch, but are being followed
if possible to get larger blocks
- idle loop recognition
- optimised literal loads, load/store cycle counting
 and loads/stores from constant addresses
2020-06-16 11:56:36 +02:00
85680d6fe5 more fixes for flag optimisation
+ small cycle counting optimisation
2020-06-16 11:56:01 +02:00
d208f5909c fixes for flag optimisation 2020-06-16 11:55:53 +02:00
f378458c10 optimise away unneeded flag sets
- especially useful for thumb code and larger max block sizes
- can still be improved upon
2020-06-16 11:55:44 +02:00
26ecf6bb3c fix register alloc for half word loads
fixes Mega Man Star Force 2 with cheat applied
it probably used a pc relative load which were interpreted as branches
2020-06-16 11:54:51 +02:00
d74b15eecc jit: fix thumb hi reg alu and mcr halt
+ mcr/mrc aren't always, msr_imm is never unk on ARM7
2020-06-16 11:54:06 +02:00
03b321f540 jit: fix misc static branch things 2020-06-16 11:54:05 +02:00
dd04cef47e jit: fix BLX_reg with rn=lr 2020-06-16 11:54:03 +02:00
83bd863361 jit: branch instructions 2020-06-16 11:53:09 +02:00
27cbc821b1 jit: thumb block transfer working
also pc and sp relative loads and some refactoring
2020-06-16 11:53:08 +02:00
10e386fe50 JIT: most mem instructions working
+ branching
2020-06-16 11:53:08 +02:00
c692287eba JIT: base
all instructions are interpreted
2020-06-16 11:53:05 +02:00