0e7df468c7
x64 JIT: generate patch trunk for RSCRATCH4
...
I thought I already fixed this?
2020-07-25 22:21:26 +02:00
3786660099
misc JIT changes
2020-07-08 23:08:25 +02:00
c5381d2911
reconcile DSi and JIT, fastmem for x64 and Windows
2020-06-30 23:50:41 +02:00
e335a8ca76
first steps in bringing over the JIT refactor/fastmem
2020-06-16 12:11:19 +02:00
4cff4b5228
allow allocating caller saved regs on windows
2020-05-09 15:39:39 +02:00
5a0b568647
allow allocating caller saved registers
...
currently system-v only
2020-05-09 14:34:52 +02:00
0f53a34551
rewrite JIT memory emulation
2020-05-09 00:45:05 +02:00
bcc4b5c8dd
fix regression from last commit
...
also a small mistake with msr
2020-04-26 23:25:32 +02:00
b0b9ec42e4
don't use param registers for ReadBanked/WriteBanked
...
should fix linux build
2020-04-26 20:47:36 +02:00
a9dd6e30ad
implement msr and mrs for the x64 JIT
2020-04-26 13:05:18 +02:00
68d552074b
compile UMULLs and some fixes
2020-04-26 13:05:17 +02:00
3787bab1f6
implement block linking + some refactoring
...
currently only supported for x64
2020-04-26 13:05:17 +02:00
5d0f244f3c
include more information in DataRegion
2020-04-26 13:05:16 +02:00
9b98b8816a
improve nop handling and proper behaviour for LDM^
...
fixes dslinux
2020-04-26 13:05:08 +02:00
81f38c14be
integrate changes from ARM64 backend and more
...
- better handle LDM/STM in reg alloc
- unify Halted and IRQ in anticipation for branch inlining
- literal optimisations can be disabled in gui
- jit blocks follow simple returns
- fix idle loop detection
- break jit blocks on IRQ (fixes saving in Pokemon White)
2020-04-26 13:05:05 +02:00
7424f9fda0
remove leftover debug code
2020-04-26 13:05:04 +02:00
a687be9879
new block cache and much more...
...
- more reliable code invalidation detection
- blocks aren't stopped at any branch, but are being followed
if possible to get larger blocks
- idle loop recognition
- optimised literal loads, load/store cycle counting
and loads/stores from constant addresses
2020-04-26 13:05:03 +02:00
5338c28f40
load register only if needed
...
- do thumb bl long merge in the first step
- preparations for better branch jitting
2020-04-26 13:05:02 +02:00
2ef776883f
more fixes for flag optimisation
...
+ small cycle counting optimisation
2020-04-26 13:05:02 +02:00
5202c505ab
remove debug printing
2020-04-26 13:05:01 +02:00
5ea91b8a03
optimise away unneeded flag sets
...
- especially useful for thumb code and larger max block sizes
- can still be improved upon
2020-04-26 13:05:00 +02:00
3001d9492c
abandon pipelining on jit
...
fixes Golden Sun Dawn
this makes the cpu state incompatible between interpreter and JIT. That's why switching cpu mode requires a restart(not requiring is stupid anyway) and the pipeline is manually filled when making a save state.
2020-04-26 13:04:59 +02:00
5e443e7962
remove unneeded dolphin code, C++11 static_assert
2020-04-26 13:04:57 +02:00
9d180c7bbc
jit: decrease blockcache AddrMapping size for ARM9
2020-04-26 13:03:09 +02:00
be8846e31a
jit: fix misc static branch things
2020-04-26 13:03:08 +02:00
411fb57c07
jit: add compile option
2020-04-26 13:03:06 +02:00
9d76d63af5
jit: make everything configurable
2020-04-26 13:03:03 +02:00
dcf6e1cad2
jit: fix linux
2020-04-26 13:03:01 +02:00
6f0dcad4f6
jit: fix wrongly placed const
2020-04-26 13:03:01 +02:00
9b3c14b58a
jit: SMULL and SMLAL
2020-04-26 13:03:00 +02:00
2efab201e9
jit: LDM/STM finally(!) working + MUL, MLA and CLZ
2020-04-26 13:02:59 +02:00
c58fdbd66b
jit: branch instructions
2020-04-26 13:02:58 +02:00
ff97211114
jit: thumb block transfer working
...
also pc and sp relative loads and some refactoring
2020-04-26 13:02:57 +02:00
2c44bf927c
JIT: most mem instructions working
...
+ branching
2020-04-26 13:02:57 +02:00
5f932cdf48
JIT: compilation of word load and store
2020-04-26 13:02:56 +02:00
ebce9f035f
JIT: implemented most ALU instructions
2020-04-26 13:02:55 +02:00
c5c342c009
JIT: base
...
all instructions are interpreted
2020-04-26 13:02:53 +02:00
