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1,501 Commits 53 Branches 22 Tags 29 MiB
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Author SHA1 Message Date
RSDuck
c8b7a34383 git played a prank on me haha very funny 2020-06-16 11:57:55 +02:00
RSDuck
262dc7ad00 this it should work 2020-06-16 11:57:55 +02:00
RSDuck
d2acceb367 fixup for aarch64 JIT 2020-06-16 11:57:54 +02:00
RSDuck
2725429727 fix LDM usermode for aarch64 as well 2020-06-16 11:57:53 +02:00
RSDuck
3173e6e25d re add error for unsupported JIT platforms 2020-06-16 11:57:52 +02:00
RSDuck
0d83e98e04 apply fixes for aarch64 linux by @nadiaholmquist 2020-06-16 11:57:52 +02:00
RSDuck
99b34efe2d move ARM64 JIT backend here 2020-06-16 11:57:51 +02:00
RSDuck
baed0ac0d5 remove debug leftovers 2020-06-16 11:57:50 +02:00
RSDuck
ec965c6014 improve nop handling and proper behaviour for LDM^ 
fixes dslinux
 2020-06-16 11:57:49 +02:00
RSDuck
000c03c9d6 disable literal optimations in DTCM 2020-06-16 11:57:48 +02:00
RSDuck
1cfbbcbb2a make savestates 100% compatible again 2020-06-16 11:57:48 +02:00
RSDuck
3e7483636f make literal optimisation more reliable 
fixes spanish Pokemon HeartGold
 2020-06-16 11:57:47 +02:00
RSDuck
d1d96d2236 fix config key for jit literal optimisations 2020-06-16 11:57:46 +02:00
RSDuck
441869a105 integrate changes from ARM64 backend and more 
- better handle LDM/STM in reg alloc
- unify Halted and IRQ in anticipation for branch inlining
- literal optimisations can be disabled in gui
- jit blocks follow simple returns
- fix idle loop detection
- break jit blocks on IRQ (fixes saving in Pokemon White)
 2020-06-16 11:57:45 +02:00
RSDuck
9cf7780e46 decrease jit block cache address granularity 
fixes Dragon Quest IX
move code with side effects out of assert, fixes release build
(thanks to m4wx for this one)
also remove some leftovers of jit pipelining
 2020-06-16 11:56:45 +02:00
RSDuck
52dd0ee75a remove leftover debug code 2020-06-16 11:56:37 +02:00
RSDuck
40b88ab05a new block cache and much more... 
- more reliable code invalidation detection
- blocks aren't stopped at any branch, but are being followed
if possible to get larger blocks
- idle loop recognition
- optimised literal loads, load/store cycle counting
 and loads/stores from constant addresses
 2020-06-16 11:56:36 +02:00
RSDuck
0e26aa4ede load register only if needed 
- do thumb bl long merge in the first step
- preparations for better branch jitting
 2020-06-16 11:56:02 +02:00
RSDuck
85680d6fe5 more fixes for flag optimisation 
+ small cycle counting optimisation
 2020-06-16 11:56:01 +02:00
RSDuck
d57ee718ba remove debug printing 2020-06-16 11:56:00 +02:00
RSDuck
d208f5909c fixes for flag optimisation 2020-06-16 11:55:53 +02:00
RSDuck
f378458c10 optimise away unneeded flag sets 
- especially useful for thumb code and larger max block sizes
- can still be improved upon
 2020-06-16 11:55:44 +02:00
RSDuck
316378092a abandon pipelining on jit 
fixes Golden Sun Dawn
this makes the cpu state incompatible between interpreter and JIT. That's why switching cpu mode requires a restart(not requiring is stupid anyway) and the pipeline is manually filled when making a save state.
 2020-06-16 11:55:24 +02:00
RSDuck
26ecf6bb3c fix register alloc for half word loads 
fixes Mega Man Star Force 2 with cheat applied
it probably used a pc relative load which were interpreted as branches
 2020-06-16 11:54:51 +02:00
RSDuck
86b96ca47a remove unneeded dolphin code, C++11 static_assert 2020-06-16 11:54:50 +02:00
Arisotura
727be0fd92 add the JIT shito to the Codeblocks project 2020-06-16 11:54:50 +02:00
RSDuck
851930f5e0 jit: fix RSC 2020-06-16 11:54:49 +02:00
RSDuck
0d786573ab remove debug printf 2020-06-16 11:54:48 +02:00
RSDuck
00cd9af033 fix uninitialised memory mapping 2020-06-16 11:54:47 +02:00
RSDuck
d74b15eecc jit: fix thumb hi reg alu and mcr halt 
+ mcr/mrc aren't always, msr_imm is never unk on ARM7
 2020-06-16 11:54:06 +02:00
RSDuck
4deecc7d65 jit: decrease blockcache AddrMapping size for ARM9 2020-06-16 11:54:05 +02:00
RSDuck
03b321f540 jit: fix misc static branch things 2020-06-16 11:54:05 +02:00
RSDuck
3167ddcde1 jit: LDM/STM keep proper stack alignment 2020-06-16 11:54:04 +02:00
RSDuck
dd04cef47e jit: fix BLX_reg with rn=lr 2020-06-16 11:54:03 +02:00
RSDuck
86f2be7260 jit: add compile option 2020-06-16 11:54:03 +02:00
RSDuck
fc82ca1a97 jit: remove unnessary files from dolphin 2020-06-16 11:53:22 +02:00
RSDuck
d13d625f73 jit: make everything configurable 2020-06-16 11:53:21 +02:00
RSDuck
0ff79ea2ad jit: fix linux 2020-06-16 11:53:11 +02:00
RSDuck
24aff49ae4 jit: fix wrongly placed const 2020-06-16 11:53:11 +02:00
RSDuck
9336fcbbe6 jit: SMULL and SMLAL 2020-06-16 11:53:10 +02:00
RSDuck
f22521a43d jit: LDM/STM finally(!) working + MUL, MLA and CLZ 2020-06-16 11:53:10 +02:00
RSDuck
83bd863361 jit: branch instructions 2020-06-16 11:53:09 +02:00
RSDuck
27cbc821b1 jit: thumb block transfer working 
also pc and sp relative loads and some refactoring
 2020-06-16 11:53:08 +02:00
RSDuck
10e386fe50 JIT: most mem instructions working 
+ branching
 2020-06-16 11:53:08 +02:00
RSDuck
550e6b86d2 JIT: compilation of word load and store 2020-06-16 11:53:07 +02:00
RSDuck
ea98a44e1e jit: correct cycle counting for thumb shift by reg 2020-06-16 11:53:06 +02:00
RSDuck
2f6b46fd4f JIT: implemented most ALU instructions 2020-06-16 11:53:06 +02:00
RSDuck
c692287eba JIT: base 
all instructions are interpreted
 2020-06-16 11:53:05 +02:00
Arisotura
aa6ff499f9 prepare JIT beta branch 2020-06-16 11:52:45 +02:00
Arisotura
1101ed773b make it get further 2020-06-16 02:52:53 +02:00