14 Commits

Author	SHA1	Message	Date
RSDuck	68d552074b	compile UMULLs and some fixes	2020-04-26 13:05:17 +02:00
RSDuck	a687be9879	new block cache and much more... ... - more reliable code invalidation detection - blocks aren't stopped at any branch, but are being followed if possible to get larger blocks - idle loop recognition - optimised literal loads, load/store cycle counting and loads/stores from constant addresses	2020-04-26 13:05:03 +02:00
RSDuck	ea562d2fec	fixes for flag optimisation	2020-04-26 13:05:01 +02:00
RSDuck	5ea91b8a03	optimise away unneeded flag sets ... - especially useful for thumb code and larger max block sizes - can still be improved upon	2020-04-26 13:05:00 +02:00
RSDuck	5e443e7962	remove unneeded dolphin code, C++11 static_assert	2020-04-26 13:04:57 +02:00
RSDuck	f31976fed0	jit: fix RSC	2020-04-26 13:03:12 +02:00
RSDuck	4a0f6b3b4b	jit: fix thumb hi reg alu and mcr halt ... + mcr/mrc aren't always, msr_imm is never unk on ARM7	2020-04-26 13:03:10 +02:00
RSDuck	dcf6e1cad2	jit: fix linux	2020-04-26 13:03:01 +02:00
RSDuck	9b3c14b58a	jit: SMULL and SMLAL	2020-04-26 13:03:00 +02:00
RSDuck	2efab201e9	jit: LDM/STM finally(!) working + MUL, MLA and CLZ	2020-04-26 13:02:59 +02:00
RSDuck	2c44bf927c	JIT: most mem instructions working ... + branching	2020-04-26 13:02:57 +02:00
RSDuck	5f932cdf48	JIT: compilation of word load and store	2020-04-26 13:02:56 +02:00
RSDuck	ff901141e7	jit: correct cycle counting for thumb shift by reg	2020-04-26 13:02:55 +02:00
RSDuck	ebce9f035f	JIT: implemented most ALU instructions	2020-04-26 13:02:55 +02:00