mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-21 21:31:00 -06:00
826 lines
24 KiB
C++
826 lines
24 KiB
C++
#include "ARMJIT_Compiler.h"
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#include "../Config.h"
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using namespace Gen;
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namespace ARMJIT
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{
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template <typename T>
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int squeezePointer(T* ptr)
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{
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int truncated = (int)((u64)ptr);
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assert((T*)((u64)truncated) == ptr);
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return truncated;
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}
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/*
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According to DeSmuME and my own research, approx. 99% (seriously, that's an empirical number)
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of all memory load and store instructions always access addresses in the same region as
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during the their first execution.
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I tried multiple optimisations, which would benefit from this behaviour
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(having fast paths for the first region, …), though none of them yielded a measureable
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improvement.
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*/
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/*
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address - ABI_PARAM1 (a.k.a. ECX = RSCRATCH3 on Windows)
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store value - ABI_PARAM2 (a.k.a. RDX = RSCRATCH2 on Windows)
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*/
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void* Compiler::Gen_MemoryRoutine9(bool store, int size)
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{
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u32 addressMask = ~(size == 32 ? 3 : (size == 16 ? 1 : 0));
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AlignCode4();
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void* res = GetWritableCodePtr();
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MOV(32, R(RSCRATCH), R(ABI_PARAM1));
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SUB(32, R(RSCRATCH), MDisp(RCPU, offsetof(ARMv5, DTCMBase)));
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CMP(32, R(RSCRATCH), MDisp(RCPU, offsetof(ARMv5, DTCMSize)));
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FixupBranch insideDTCM = J_CC(CC_B);
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CMP(32, R(ABI_PARAM1), MDisp(RCPU, offsetof(ARMv5, ITCMSize)));
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FixupBranch insideITCM = J_CC(CC_B);
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if (store)
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{
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if (size > 8)
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AND(32, R(ABI_PARAM1), Imm32(addressMask));
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switch (size)
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{
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case 32: JMP((u8*)NDS::ARM9Write32, true); break;
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case 16: JMP((u8*)NDS::ARM9Write16, true); break;
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case 8: JMP((u8*)NDS::ARM9Write8, true); break;
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}
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}
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else
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{
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if (size == 32)
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{
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ABI_PushRegistersAndAdjustStack({ABI_PARAM1}, 8);
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AND(32, R(ABI_PARAM1), Imm32(addressMask));
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// everything's already in the appropriate register
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ABI_CallFunction(NDS::ARM9Read32);
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ABI_PopRegistersAndAdjustStack({ECX}, 8);
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AND(32, R(ECX), Imm8(3));
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SHL(32, R(ECX), Imm8(3));
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ROR_(32, R(RSCRATCH), R(ECX));
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RET();
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}
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else if (size == 16)
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{
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AND(32, R(ABI_PARAM1), Imm32(addressMask));
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JMP((u8*)NDS::ARM9Read16, true);
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}
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else
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JMP((u8*)NDS::ARM9Read8, true);
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}
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SetJumpTarget(insideDTCM);
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AND(32, R(RSCRATCH), Imm32(0x3FFF & addressMask));
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if (store)
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MOV(size, MComplex(RCPU, RSCRATCH, SCALE_1, offsetof(ARMv5, DTCM)), R(ABI_PARAM2));
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else
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{
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MOVZX(32, size, RSCRATCH, MComplex(RCPU, RSCRATCH, SCALE_1, offsetof(ARMv5, DTCM)));
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if (size == 32)
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{
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if (ABI_PARAM1 != ECX)
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MOV(32, R(ECX), R(ABI_PARAM1));
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AND(32, R(ECX), Imm8(3));
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SHL(32, R(ECX), Imm8(3));
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ROR_(32, R(RSCRATCH), R(ECX));
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}
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}
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RET();
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SetJumpTarget(insideITCM);
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MOV(32, R(ABI_PARAM3), R(ABI_PARAM1)); // free up ECX
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AND(32, R(ABI_PARAM3), Imm32(0x7FFF & addressMask));
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if (store)
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{
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MOV(size, MComplex(RCPU, ABI_PARAM3, SCALE_1, offsetof(ARMv5, ITCM)), R(ABI_PARAM2));
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// if CodeRanges[pseudoPhysical/256].Blocks.Length > 0 we're writing into code!
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static_assert(sizeof(AddressRange) == 16);
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LEA(32, ABI_PARAM1, MDisp(ABI_PARAM3, ExeMemRegionOffsets[exeMem_ITCM]));
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MOV(32, R(RSCRATCH), R(ABI_PARAM1));
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SHR(32, R(RSCRATCH), Imm8(9));
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SHL(32, R(RSCRATCH), Imm8(4));
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CMP(16, MDisp(RSCRATCH, squeezePointer(CodeRanges) + offsetof(AddressRange, Blocks.Length)), Imm8(0));
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FixupBranch noCode = J_CC(CC_Z);
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JMP((u8*)InvalidateByAddr, true);
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SetJumpTarget(noCode);
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}
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else
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{
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MOVZX(32, size, RSCRATCH, MComplex(RCPU, ABI_PARAM3, SCALE_1, offsetof(ARMv5, ITCM)));
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if (size == 32)
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{
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if (ABI_PARAM1 != ECX)
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MOV(32, R(ECX), R(ABI_PARAM1));
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AND(32, R(ECX), Imm8(3));
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SHL(32, R(ECX), Imm8(3));
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ROR_(32, R(RSCRATCH), R(ECX));
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}
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}
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RET();
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static_assert(RSCRATCH == EAX, "Someone changed RSCRATCH!");
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return res;
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}
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#define MEMORY_SEQ_WHILE_COND \
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if (!store) \
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MOV(32, currentElement, R(EAX));\
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if (!preinc) \
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ADD(32, R(ABI_PARAM1), Imm8(4)); \
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\
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SUB(32, R(ABI_PARAM3), Imm8(1)); \
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J_CC(CC_NZ, repeat);
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/*
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ABI_PARAM1 address
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ABI_PARAM2 address where registers are stored
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ABI_PARAM3 how many values to read/write
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Dolphin x64CodeEmitter is my favourite assembler
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*/
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void* Compiler::Gen_MemoryRoutineSeq9(bool store, bool preinc)
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{
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void* res = (void*)GetWritableCodePtr();
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const u8* repeat = GetCodePtr();
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if (preinc)
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ADD(32, R(ABI_PARAM1), Imm8(4));
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MOV(32, R(RSCRATCH), R(ABI_PARAM1));
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SUB(32, R(RSCRATCH), MDisp(RCPU, offsetof(ARMv5, DTCMBase)));
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CMP(32, R(RSCRATCH), MDisp(RCPU, offsetof(ARMv5, DTCMSize)));
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FixupBranch insideDTCM = J_CC(CC_B);
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CMP(32, R(ABI_PARAM1), MDisp(RCPU, offsetof(ARMv5, ITCMSize)));
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FixupBranch insideITCM = J_CC(CC_B);
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OpArg currentElement = MComplex(ABI_PARAM2, ABI_PARAM3, SCALE_8, -8); // wasting stack space like a gangster
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ABI_PushRegistersAndAdjustStack({ABI_PARAM1, ABI_PARAM2, ABI_PARAM3}, 8);
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AND(32, R(ABI_PARAM1), Imm8(~3));
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if (store)
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{
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MOV(32, R(ABI_PARAM2), currentElement);
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CALL((void*)NDS::ARM9Write32);
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}
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else
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CALL((void*)NDS::ARM9Read32);
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ABI_PopRegistersAndAdjustStack({ABI_PARAM1, ABI_PARAM2, ABI_PARAM3}, 8);
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MEMORY_SEQ_WHILE_COND
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RET();
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SetJumpTarget(insideDTCM);
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AND(32, R(RSCRATCH), Imm32(0x3FFF & ~3));
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if (store)
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{
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MOV(32, R(ABI_PARAM4), currentElement);
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MOV(32, MComplex(RCPU, RSCRATCH, SCALE_1, offsetof(ARMv5, DTCM)), R(ABI_PARAM4));
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}
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else
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MOV(32, R(RSCRATCH), MComplex(RCPU, RSCRATCH, SCALE_1, offsetof(ARMv5, DTCM)));
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MEMORY_SEQ_WHILE_COND
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RET();
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SetJumpTarget(insideITCM);
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MOV(32, R(RSCRATCH), R(ABI_PARAM1));
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AND(32, R(RSCRATCH), Imm32(0x7FFF & ~3));
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if (store)
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{
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MOV(32, R(ABI_PARAM4), currentElement);
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MOV(32, MComplex(RCPU, RSCRATCH, SCALE_1, offsetof(ARMv5, ITCM)), R(ABI_PARAM4));
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ADD(32, R(RSCRATCH), Imm32(ExeMemRegionOffsets[exeMem_ITCM]));
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MOV(32, R(ABI_PARAM4), R(RSCRATCH));
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SHR(32, R(RSCRATCH), Imm8(9));
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SHL(32, R(RSCRATCH), Imm8(4));
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CMP(16, MDisp(RSCRATCH, squeezePointer(CodeRanges) + offsetof(AddressRange, Blocks.Length)), Imm8(0));
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FixupBranch noCode = J_CC(CC_Z);
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ABI_PushRegistersAndAdjustStack({ABI_PARAM1, ABI_PARAM2, ABI_PARAM3}, 8);
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MOV(32, R(ABI_PARAM1), R(ABI_PARAM4));
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CALL((u8*)InvalidateByAddr);
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ABI_PopRegistersAndAdjustStack({ABI_PARAM1, ABI_PARAM2, ABI_PARAM3}, 8);
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SetJumpTarget(noCode);
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}
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else
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MOV(32, R(RSCRATCH), MComplex(RCPU, RSCRATCH, SCALE_1, offsetof(ARMv5, ITCM)));
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MEMORY_SEQ_WHILE_COND
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RET();
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return res;
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}
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void* Compiler::Gen_MemoryRoutineSeq7(bool store, bool preinc, bool codeMainRAM)
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{
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void* res = (void*)GetWritableCodePtr();
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const u8* repeat = GetCodePtr();
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if (preinc)
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ADD(32, R(ABI_PARAM1), Imm8(4));
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OpArg currentElement = MComplex(ABI_PARAM2, ABI_PARAM3, SCALE_8, -8);
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ABI_PushRegistersAndAdjustStack({ABI_PARAM1, ABI_PARAM2, ABI_PARAM3}, 8);
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AND(32, R(ABI_PARAM1), Imm8(~3));
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if (store)
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{
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MOV(32, R(ABI_PARAM2), currentElement);
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CALL((void*)NDS::ARM7Write32);
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}
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else
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CALL((void*)NDS::ARM7Read32);
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ABI_PopRegistersAndAdjustStack({ABI_PARAM1, ABI_PARAM2, ABI_PARAM3}, 8);
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MEMORY_SEQ_WHILE_COND
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RET();
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return res;
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}
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#undef MEMORY_SEQ_WHILE_COND
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void Compiler::Comp_MemLoadLiteral(int size, int rd, u32 addr)
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{
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u32 val;
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// make sure arm7 bios is accessible
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u32 tmpR15 = CurCPU->R[15];
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CurCPU->R[15] = R15;
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if (size == 32)
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{
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CurCPU->DataRead32(addr & ~0x3, &val);
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val = ROR(val, (addr & 0x3) << 3);
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}
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else if (size == 16)
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CurCPU->DataRead16(addr & ~0x1, &val);
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else
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CurCPU->DataRead8(addr, &val);
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CurCPU->R[15] = tmpR15;
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MOV(32, MapReg(rd), Imm32(val));
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if (Thumb || CurInstr.Cond() == 0xE)
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RegCache.PutLiteral(rd, val);
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Comp_AddCycles_CDI();
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}
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/*void fault(u32 a, u32 b, u32 c, u32 d)
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{
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printf("actually not static! %x %x %x %x\n", a, b, c, d);
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}*/
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void Compiler::Comp_MemAccess(int rd, int rn, const ComplexOperand& op2, int size, int flags)
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{
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u32 addressMask = ~0;
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if (size == 32)
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addressMask = ~3;
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if (size == 16)
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addressMask = ~1;
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//bool check = false;
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if (Config::JIT_LiteralOptimisations && rn == 15 && rd != 15 && op2.IsImm && !(flags & (memop_SignExtend|memop_Post|memop_Store|memop_Writeback)))
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{
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u32 addr = R15 + op2.Imm * ((flags & memop_SubtractOffset) ? -1 : 1);
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u32 translatedAddr = Num == 0 ? TranslateAddr<0>(addr) : TranslateAddr<1>(addr);
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if (!(CodeRanges[translatedAddr / 512].InvalidLiterals & (1 << ((translatedAddr & 0x1FF) / 16))))
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{
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Comp_MemLoadLiteral(size, rd, addr);
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return;
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}
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}
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{
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if (flags & memop_Store)
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{
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Comp_AddCycles_CD();
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}
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else
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{
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Comp_AddCycles_CDI();
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}
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OpArg rdMapped = MapReg(rd);
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OpArg rnMapped = MapReg(rn);
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if (Thumb && rn == 15)
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rnMapped = Imm32(R15 & ~0x2);
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bool inlinePreparation = Num == 1;
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u32 constLocalROR32 = 4;
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void* memoryFunc = Num == 0
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? MemoryFuncs9[size >> 4][!!(flags & memop_Store)]
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: MemoryFuncs7[size >> 4][!!((flags & memop_Store))];
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if (Config::JIT_LiteralOptimisations && (rd != 15 || (flags & memop_Store)) && op2.IsImm && RegCache.IsLiteral(rn))
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{
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u32 addr = RegCache.LiteralValues[rn] + op2.Imm * ((flags & memop_SubtractOffset) ? -1 : 1);
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/*MOV(32, R(ABI_PARAM1), Imm32(CurInstr.Instr));
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MOV(32, R(ABI_PARAM1), Imm32(R15));
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MOV_sum(32, RSCRATCH, rnMapped, Imm32(op2.Imm * ((flags & memop_SubtractOffset) ? -1 : 1)));
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CMP(32, R(RSCRATCH), Imm32(addr));
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FixupBranch eq = J_CC(CC_E);
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CALL((void*)fault);
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SetJumpTarget(eq);*/
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NDS::MemRegion region;
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region.Mem = NULL;
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if (Num == 0)
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{
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ARMv5* cpu5 = (ARMv5*)CurCPU;
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// stupid dtcm...
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if (addr >= cpu5->DTCMBase && addr < (cpu5->DTCMBase + cpu5->DTCMSize))
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{
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// disable this for now as DTCM is located in heap
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// which might excced the RIP-addressable range
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//region.Mem = cpu5->DTCM;
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//region.Mask = 0x3FFF;
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}
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else
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{
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NDS::ARM9GetMemRegion(addr, flags & memop_Store, ®ion);
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}
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}
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else
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NDS::ARM7GetMemRegion(addr, flags & memop_Store, ®ion);
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if (region.Mem != NULL)
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{
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void* ptr = ®ion.Mem[addr & addressMask & region.Mask];
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if (flags & memop_Store)
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{
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MOV(size, M(ptr), MapReg(rd));
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}
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else
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{
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if (flags & memop_SignExtend)
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MOVSX(32, size, rdMapped.GetSimpleReg(), M(ptr));
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else
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MOVZX(32, size, rdMapped.GetSimpleReg(), M(ptr));
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if (size == 32 && addr & ~0x3)
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{
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ROR_(32, rdMapped, Imm8((addr & 0x3) << 3));
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}
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}
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return;
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}
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void* specialFunc = GetFuncForAddr(CurCPU, addr, flags & memop_Store, size);
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if (specialFunc)
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{
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memoryFunc = specialFunc;
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inlinePreparation = true;
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constLocalROR32 = addr & 0x3;
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}
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}
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X64Reg finalAddr = ABI_PARAM1;
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if (flags & memop_Post)
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{
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MOV(32, R(ABI_PARAM1), rnMapped);
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finalAddr = rnMapped.GetSimpleReg();
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}
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if (op2.IsImm)
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{
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MOV_sum(32, finalAddr, rnMapped, Imm32(op2.Imm * ((flags & memop_SubtractOffset) ? -1 : 1)));
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}
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else
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{
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OpArg rm = MapReg(op2.Reg.Reg);
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if (!(flags & memop_SubtractOffset) && rm.IsSimpleReg() && rnMapped.IsSimpleReg()
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&& op2.Reg.Op == 0 && op2.Reg.Amount > 0 && op2.Reg.Amount <= 3)
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{
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LEA(32, finalAddr,
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MComplex(rnMapped.GetSimpleReg(), rm.GetSimpleReg(), 1 << op2.Reg.Amount, 0));
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}
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else
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{
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bool throwAway;
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OpArg offset =
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Comp_RegShiftImm(op2.Reg.Op, op2.Reg.Amount, rm, false, throwAway);
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if (flags & memop_SubtractOffset)
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{
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if (R(finalAddr) != rnMapped)
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MOV(32, R(finalAddr), rnMapped);
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if (!offset.IsZero())
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SUB(32, R(finalAddr), offset);
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}
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else
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MOV_sum(32, finalAddr, rnMapped, offset);
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}
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}
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if ((flags & memop_Writeback) && !(flags & memop_Post))
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MOV(32, rnMapped, R(finalAddr));
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if (flags & memop_Store)
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MOV(32, R(ABI_PARAM2), rdMapped);
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if (!(flags & memop_Store) && inlinePreparation && constLocalROR32 == 4 && size == 32)
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MOV(32, rdMapped, R(ABI_PARAM1));
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if (inlinePreparation && size > 8)
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AND(32, R(ABI_PARAM1), Imm8(addressMask));
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CALL(memoryFunc);
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/*if (Num == 0 && check)
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{
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CMP(32, R(EAX), rdMapped);
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FixupBranch notEqual = J_CC(CC_E);
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ABI_PushRegistersAndAdjustStack({RSCRATCH}, 0);
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MOV(32, R(ABI_PARAM1), Imm32(R15 - (Thumb ? 4 : 8)));
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MOV(32, R(ABI_PARAM2), R(EAX));
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MOV(32, R(ABI_PARAM3), rdMapped);
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MOV(32, R(ABI_PARAM4), Imm32(CurInstr.Instr));
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CALL((u8*)fault);
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ABI_PopRegistersAndAdjustStack({RSCRATCH}, 0);
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SetJumpTarget(notEqual);
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}*/
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if (!(flags & memop_Store))
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{
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if (inlinePreparation && size == 32)
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{
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if (constLocalROR32 == 4)
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{
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static_assert(RSCRATCH3 == ECX);
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MOV(32, R(ECX), rdMapped);
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AND(32, R(ECX), Imm8(3));
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SHL(32, R(ECX), Imm8(3));
|
|
ROR_(32, R(RSCRATCH), R(ECX));
|
|
}
|
|
else if (constLocalROR32 != 0)
|
|
ROR_(32, R(RSCRATCH), Imm8(constLocalROR32 << 3));
|
|
}
|
|
|
|
if (flags & memop_SignExtend)
|
|
MOVSX(32, size, rdMapped.GetSimpleReg(), R(RSCRATCH));
|
|
else
|
|
MOVZX(32, size, rdMapped.GetSimpleReg(), R(RSCRATCH));
|
|
}
|
|
|
|
if (!(flags & memop_Store) && rd == 15)
|
|
{
|
|
if (size < 32)
|
|
printf("!!! LDR <32 bit PC %08X %x\n", R15, CurInstr.Instr);
|
|
{
|
|
if (Num == 1)
|
|
AND(32, rdMapped, Imm8(0xFE)); // immediate is sign extended
|
|
Comp_JumpTo(rdMapped.GetSimpleReg());
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
s32 Compiler::Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc, bool decrement, bool usermode)
|
|
{
|
|
IrregularCycles = true;
|
|
|
|
int regsCount = regs.Count();
|
|
|
|
if (decrement)
|
|
{
|
|
MOV_sum(32, ABI_PARAM1, MapReg(rn), Imm32(-regsCount * 4));
|
|
preinc ^= true;
|
|
}
|
|
else
|
|
MOV(32, R(ABI_PARAM1), MapReg(rn));
|
|
|
|
s32 offset = (regsCount * 4) * (decrement ? -1 : 1);
|
|
|
|
// we need to make sure that the stack stays aligned to 16 bytes
|
|
u32 stackAlloc = ((regsCount + 1) & ~1) * 8;
|
|
|
|
if (!store)
|
|
{
|
|
Comp_AddCycles_CDI();
|
|
|
|
MOV(32, R(ABI_PARAM3), Imm32(regsCount));
|
|
SUB(64, R(RSP), stackAlloc <= INT8_MAX ? Imm8(stackAlloc) : Imm32(stackAlloc));
|
|
MOV(64, R(ABI_PARAM2), R(RSP));
|
|
|
|
CALL(Num == 0
|
|
? MemoryFuncsSeq9[0][preinc]
|
|
: MemoryFuncsSeq7[0][preinc][CodeRegion == 0x02]);
|
|
|
|
bool firstUserMode = true;
|
|
for (int reg = 15; reg >= 0; reg--)
|
|
{
|
|
if (regs[reg])
|
|
{
|
|
if (usermode && !regs[15] && reg >= 8 && reg < 15)
|
|
{
|
|
if (firstUserMode)
|
|
{
|
|
MOV(32, R(RSCRATCH), R(RCPSR));
|
|
AND(32, R(RSCRATCH), Imm8(0x1F));
|
|
firstUserMode = false;
|
|
}
|
|
MOV(32, R(RSCRATCH2), Imm32(reg - 8));
|
|
POP(RSCRATCH3);
|
|
CALL(WriteBanked);
|
|
FixupBranch sucessfulWritten = J_CC(CC_NC);
|
|
if (RegCache.Mapping[reg] != INVALID_REG)
|
|
MOV(32, R(RegCache.Mapping[reg]), R(RSCRATCH3));
|
|
else
|
|
SaveReg(reg, RSCRATCH3);
|
|
SetJumpTarget(sucessfulWritten);
|
|
}
|
|
else if (RegCache.Mapping[reg] == INVALID_REG)
|
|
{
|
|
assert(reg != 15);
|
|
|
|
POP(RSCRATCH);
|
|
SaveReg(reg, RSCRATCH);
|
|
}
|
|
else
|
|
{
|
|
if (reg != 15)
|
|
RegCache.DirtyRegs |= (1 << reg);
|
|
POP(MapReg(reg).GetSimpleReg());
|
|
}
|
|
}
|
|
}
|
|
|
|
if (regsCount & 1)
|
|
POP(RSCRATCH);
|
|
|
|
if (regs[15])
|
|
{
|
|
if (Num == 1)
|
|
{
|
|
if (Thumb)
|
|
OR(32, MapReg(15), Imm8(1));
|
|
else
|
|
AND(32, MapReg(15), Imm8(0xFE));
|
|
}
|
|
Comp_JumpTo(MapReg(15).GetSimpleReg(), usermode);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
Comp_AddCycles_CD();
|
|
|
|
if (regsCount & 1)
|
|
PUSH(RSCRATCH);
|
|
|
|
bool firstUserMode = true;
|
|
for (int reg : regs)
|
|
{
|
|
if (usermode && reg >= 8 && reg < 15)
|
|
{
|
|
if (firstUserMode)
|
|
{
|
|
MOV(32, R(RSCRATCH), R(RCPSR));
|
|
AND(32, R(RSCRATCH), Imm8(0x1F));
|
|
firstUserMode = false;
|
|
}
|
|
if (RegCache.Mapping[reg] == INVALID_REG)
|
|
LoadReg(reg, RSCRATCH3);
|
|
else
|
|
MOV(32, R(RSCRATCH3), R(RegCache.Mapping[reg]));
|
|
MOV(32, R(RSCRATCH2), Imm32(reg - 8));
|
|
CALL(ReadBanked);
|
|
PUSH(RSCRATCH3);
|
|
}
|
|
else if (RegCache.Mapping[reg] == INVALID_REG)
|
|
{
|
|
LoadReg(reg, RSCRATCH);
|
|
PUSH(RSCRATCH);
|
|
}
|
|
else
|
|
{
|
|
PUSH(MapReg(reg).GetSimpleReg());
|
|
}
|
|
}
|
|
|
|
MOV(64, R(ABI_PARAM2), R(RSP));
|
|
MOV(32, R(ABI_PARAM3), Imm32(regsCount));
|
|
|
|
CALL(Num == 0
|
|
? MemoryFuncsSeq9[1][preinc]
|
|
: MemoryFuncsSeq7[1][preinc][CodeRegion == 0x02]);
|
|
|
|
ADD(64, R(RSP), stackAlloc <= INT8_MAX ? Imm8(stackAlloc) : Imm32(stackAlloc));
|
|
}
|
|
|
|
return offset;
|
|
}
|
|
|
|
|
|
void Compiler::A_Comp_MemWB()
|
|
{
|
|
bool load = CurInstr.Instr & (1 << 20);
|
|
bool byte = CurInstr.Instr & (1 << 22);
|
|
int size = byte ? 8 : 32;
|
|
|
|
int flags = 0;
|
|
if (!load)
|
|
flags |= memop_Store;
|
|
if (!(CurInstr.Instr & (1 << 24)))
|
|
flags |= memop_Post;
|
|
if (CurInstr.Instr & (1 << 21))
|
|
flags |= memop_Writeback;
|
|
if (!(CurInstr.Instr & (1 << 23)))
|
|
flags |= memop_SubtractOffset;
|
|
|
|
ComplexOperand offset;
|
|
if (!(CurInstr.Instr & (1 << 25)))
|
|
{
|
|
offset = ComplexOperand(CurInstr.Instr & 0xFFF);
|
|
}
|
|
else
|
|
{
|
|
int op = (CurInstr.Instr >> 5) & 0x3;
|
|
int amount = (CurInstr.Instr >> 7) & 0x1F;
|
|
int rm = CurInstr.A_Reg(0);
|
|
|
|
offset = ComplexOperand(rm, op, amount);
|
|
}
|
|
|
|
Comp_MemAccess(CurInstr.A_Reg(12), CurInstr.A_Reg(16), offset, size, flags);
|
|
}
|
|
|
|
void Compiler::A_Comp_MemHalf()
|
|
{
|
|
ComplexOperand offset = CurInstr.Instr & (1 << 22)
|
|
? ComplexOperand(CurInstr.Instr & 0xF | ((CurInstr.Instr >> 4) & 0xF0))
|
|
: ComplexOperand(CurInstr.A_Reg(0), 0, 0);
|
|
|
|
int op = (CurInstr.Instr >> 5) & 0x3;
|
|
bool load = CurInstr.Instr & (1 << 20);
|
|
|
|
bool signExtend = false;
|
|
int size;
|
|
if (!load)
|
|
{
|
|
size = op == 1 ? 16 : 32;
|
|
load = op == 2;
|
|
}
|
|
else if (load)
|
|
{
|
|
size = op == 2 ? 8 : 16;
|
|
signExtend = op > 1;
|
|
}
|
|
|
|
if (size == 32 && Num == 1)
|
|
return; // NOP
|
|
|
|
int flags = 0;
|
|
if (signExtend)
|
|
flags |= memop_SignExtend;
|
|
if (!load)
|
|
flags |= memop_Store;
|
|
if (!(CurInstr.Instr & (1 << 24)))
|
|
flags |= memop_Post;
|
|
if (!(CurInstr.Instr & (1 << 23)))
|
|
flags |= memop_SubtractOffset;
|
|
if (CurInstr.Instr & (1 << 21))
|
|
flags |= memop_Writeback;
|
|
|
|
Comp_MemAccess(CurInstr.A_Reg(12), CurInstr.A_Reg(16), offset, size, flags);
|
|
}
|
|
|
|
void Compiler::T_Comp_MemReg()
|
|
{
|
|
int op = (CurInstr.Instr >> 10) & 0x3;
|
|
bool load = op & 0x2;
|
|
bool byte = op & 0x1;
|
|
|
|
Comp_MemAccess(CurInstr.T_Reg(0), CurInstr.T_Reg(3), ComplexOperand(CurInstr.T_Reg(6), 0, 0),
|
|
byte ? 8 : 32, load ? 0 : memop_Store);
|
|
}
|
|
|
|
void Compiler::A_Comp_LDM_STM()
|
|
{
|
|
BitSet16 regs(CurInstr.Instr & 0xFFFF);
|
|
|
|
bool load = CurInstr.Instr & (1 << 20);
|
|
bool pre = CurInstr.Instr & (1 << 24);
|
|
bool add = CurInstr.Instr & (1 << 23);
|
|
bool writeback = CurInstr.Instr & (1 << 21);
|
|
bool usermode = CurInstr.Instr & (1 << 22);
|
|
|
|
OpArg rn = MapReg(CurInstr.A_Reg(16));
|
|
|
|
s32 offset = Comp_MemAccessBlock(CurInstr.A_Reg(16), regs, !load, pre, !add, usermode);
|
|
|
|
if (load && writeback && regs[CurInstr.A_Reg(16)])
|
|
writeback = Num == 0
|
|
? (!(regs & ~BitSet16(1 << CurInstr.A_Reg(16)))) || (regs & ~BitSet16((2 << CurInstr.A_Reg(16)) - 1))
|
|
: false;
|
|
if (writeback)
|
|
ADD(32, rn, offset >= INT8_MIN && offset < INT8_MAX ? Imm8(offset) : Imm32(offset));
|
|
}
|
|
|
|
void Compiler::T_Comp_MemImm()
|
|
{
|
|
int op = (CurInstr.Instr >> 11) & 0x3;
|
|
bool load = op & 0x1;
|
|
bool byte = op & 0x2;
|
|
u32 offset = ((CurInstr.Instr >> 6) & 0x1F) * (byte ? 1 : 4);
|
|
|
|
Comp_MemAccess(CurInstr.T_Reg(0), CurInstr.T_Reg(3), ComplexOperand(offset),
|
|
byte ? 8 : 32, load ? 0 : memop_Store);
|
|
}
|
|
|
|
void Compiler::T_Comp_MemRegHalf()
|
|
{
|
|
int op = (CurInstr.Instr >> 10) & 0x3;
|
|
bool load = op != 0;
|
|
int size = op != 1 ? 16 : 8;
|
|
bool signExtend = op & 1;
|
|
|
|
int flags = 0;
|
|
if (signExtend)
|
|
flags |= memop_SignExtend;
|
|
if (!load)
|
|
flags |= memop_Store;
|
|
|
|
Comp_MemAccess(CurInstr.T_Reg(0), CurInstr.T_Reg(3), ComplexOperand(CurInstr.T_Reg(6), 0, 0),
|
|
size, flags);
|
|
}
|
|
|
|
void Compiler::T_Comp_MemImmHalf()
|
|
{
|
|
u32 offset = (CurInstr.Instr >> 5) & 0x3E;
|
|
bool load = CurInstr.Instr & (1 << 11);
|
|
|
|
Comp_MemAccess(CurInstr.T_Reg(0), CurInstr.T_Reg(3), ComplexOperand(offset), 16,
|
|
load ? 0 : memop_Store);
|
|
}
|
|
|
|
void Compiler::T_Comp_LoadPCRel()
|
|
{
|
|
u32 offset = (CurInstr.Instr & 0xFF) << 2;
|
|
u32 addr = (R15 & ~0x2) + offset;
|
|
if (Config::JIT_LiteralOptimisations)
|
|
Comp_MemLoadLiteral(32, CurInstr.T_Reg(8), addr);
|
|
else
|
|
Comp_MemAccess(CurInstr.T_Reg(8), 15, ComplexOperand(offset), 32, 0);
|
|
}
|
|
|
|
void Compiler::T_Comp_MemSPRel()
|
|
{
|
|
u32 offset = (CurInstr.Instr & 0xFF) * 4;
|
|
bool load = CurInstr.Instr & (1 << 11);
|
|
|
|
Comp_MemAccess(CurInstr.T_Reg(8), 13, ComplexOperand(offset), 32,
|
|
load ? 0 : memop_Store);
|
|
}
|
|
|
|
void Compiler::T_Comp_PUSH_POP()
|
|
{
|
|
bool load = CurInstr.Instr & (1 << 11);
|
|
BitSet16 regs(CurInstr.Instr & 0xFF);
|
|
if (CurInstr.Instr & (1 << 8))
|
|
{
|
|
if (load)
|
|
regs[15] = true;
|
|
else
|
|
regs[14] = true;
|
|
}
|
|
|
|
OpArg sp = MapReg(13);
|
|
s32 offset = Comp_MemAccessBlock(13, regs, !load, !load, !load, false);
|
|
|
|
ADD(32, sp, Imm8(offset)); // offset will be always be in range since PUSH accesses 9 regs max
|
|
}
|
|
|
|
void Compiler::T_Comp_LDMIA_STMIA()
|
|
{
|
|
BitSet16 regs(CurInstr.Instr & 0xFF);
|
|
OpArg rb = MapReg(CurInstr.T_Reg(8));
|
|
bool load = CurInstr.Instr & (1 << 11);
|
|
|
|
s32 offset = Comp_MemAccessBlock(CurInstr.T_Reg(8), regs, !load, false, false, false);
|
|
|
|
if (!load || !regs[CurInstr.T_Reg(8)])
|
|
ADD(32, rb, Imm8(offset));
|
|
}
|
|
|
|
} |