19 Commits

Author	SHA1	Message	Date
RSDuck	b0b9ec42e4	don't use param registers for ReadBanked/WriteBanked ... should fix linux build	2020-04-26 20:47:36 +02:00
RSDuck	68d552074b	compile UMULLs and some fixes	2020-04-26 13:05:17 +02:00
RSDuck	9b98b8816a	improve nop handling and proper behaviour for LDM^ ... fixes dslinux	2020-04-26 13:05:08 +02:00
RSDuck	60650fa82e	disable literal optimations in DTCM	2020-04-26 13:05:07 +02:00
RSDuck	386100c053	make literal optimisation more reliable ... fixes spanish Pokemon HeartGold	2020-04-26 13:05:06 +02:00
RSDuck	81f38c14be	integrate changes from ARM64 backend and more ... - better handle LDM/STM in reg alloc - unify Halted and IRQ in anticipation for branch inlining - literal optimisations can be disabled in gui - jit blocks follow simple returns - fix idle loop detection - break jit blocks on IRQ (fixes saving in Pokemon White)	2020-04-26 13:05:05 +02:00
RSDuck	aa23f21b8d	decrease jit block cache address granularity ... fixes Dragon Quest IX move code with side effects out of assert, fixes release build (thanks to m4wx for this one) also remove some leftovers of jit pipelining	2020-04-26 13:05:05 +02:00
RSDuck	a687be9879	new block cache and much more... ... - more reliable code invalidation detection - blocks aren't stopped at any branch, but are being followed if possible to get larger blocks - idle loop recognition - optimised literal loads, load/store cycle counting and loads/stores from constant addresses	2020-04-26 13:05:03 +02:00
RSDuck	2ef776883f	more fixes for flag optimisation ... + small cycle counting optimisation	2020-04-26 13:05:02 +02:00
RSDuck	3001d9492c	abandon pipelining on jit ... fixes Golden Sun Dawn this makes the cpu state incompatible between interpreter and JIT. That's why switching cpu mode requires a restart(not requiring is stupid anyway) and the pipeline is manually filled when making a save state.	2020-04-26 13:04:59 +02:00
RSDuck	5e443e7962	remove unneeded dolphin code, C++11 static_assert	2020-04-26 13:04:57 +02:00
RSDuck	54985be157	jit: LDM/STM keep proper stack alignment	2020-04-26 13:03:08 +02:00
RSDuck	dcf6e1cad2	jit: fix linux	2020-04-26 13:03:01 +02:00
RSDuck	2efab201e9	jit: LDM/STM finally(!) working + MUL, MLA and CLZ	2020-04-26 13:02:59 +02:00
RSDuck	c58fdbd66b	jit: branch instructions	2020-04-26 13:02:58 +02:00
RSDuck	ff97211114	jit: thumb block transfer working ... also pc and sp relative loads and some refactoring	2020-04-26 13:02:57 +02:00
RSDuck	2c44bf927c	JIT: most mem instructions working ... + branching	2020-04-26 13:02:57 +02:00
RSDuck	5f932cdf48	JIT: compilation of word load and store	2020-04-26 13:02:56 +02:00
RSDuck	ff901141e7	jit: correct cycle counting for thumb shift by reg	2020-04-26 13:02:55 +02:00