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Merge pull request #9770 from JosJuice/jits-accidental-gt
Jits: Fix accidentally setting GT in CR when clearing EQ
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commit
89af7b82f2
@ -116,6 +116,7 @@ public:
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void SetCRFieldBit(int field, int bit, Gen::X64Reg in);
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void ClearCRFieldBit(int field, int bit);
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void SetCRFieldBit(int field, int bit);
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void FixGTBeforeSettingCRFieldBit(Gen::X64Reg reg);
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// Generates a branch that will check if a given bit of a CR register part
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// is set or not.
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@ -54,16 +54,8 @@ void Jit64::SetCRFieldBit(int field, int bit, X64Reg in)
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MOV(64, R(RSCRATCH2), CROffset(field));
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MOVZX(32, 8, in, R(in));
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// Gross but necessary; if the input is totally zero and we set SO or LT,
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// or even just add the (1<<32), GT will suddenly end up set without us
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// intending to. This can break actual games, so fix it up.
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if (bit != PowerPC::CR_GT_BIT)
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{
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TEST(64, R(RSCRATCH2), R(RSCRATCH2));
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FixupBranch dont_clear_gt = J_CC(CC_NZ);
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BTS(64, R(RSCRATCH2), Imm8(63));
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SetJumpTarget(dont_clear_gt);
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}
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FixGTBeforeSettingCRFieldBit(RSCRATCH2);
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switch (bit)
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{
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@ -107,7 +99,10 @@ void Jit64::ClearCRFieldBit(int field, int bit)
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break;
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case PowerPC::CR_EQ_BIT:
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OR(64, CROffset(field), Imm8(1));
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MOV(64, R(RSCRATCH), CROffset(field));
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FixGTBeforeSettingCRFieldBit(RSCRATCH);
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OR(64, R(RSCRATCH), Imm8(1));
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MOV(64, CROffset(field), R(RSCRATCH));
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break;
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case PowerPC::CR_GT_BIT:
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@ -126,12 +121,7 @@ void Jit64::SetCRFieldBit(int field, int bit)
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{
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MOV(64, R(RSCRATCH), CROffset(field));
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if (bit != PowerPC::CR_GT_BIT)
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{
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TEST(64, R(RSCRATCH), R(RSCRATCH));
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FixupBranch dont_clear_gt = J_CC(CC_NZ);
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BTS(64, R(RSCRATCH), Imm8(63));
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SetJumpTarget(dont_clear_gt);
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}
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FixGTBeforeSettingCRFieldBit(RSCRATCH);
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switch (bit)
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{
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@ -157,6 +147,17 @@ void Jit64::SetCRFieldBit(int field, int bit)
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MOV(64, CROffset(field), R(RSCRATCH));
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}
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void Jit64::FixGTBeforeSettingCRFieldBit(Gen::X64Reg reg)
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{
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// Gross but necessary; if the input is totally zero and we set SO or LT,
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// or even just add the (1<<32), GT will suddenly end up set without us
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// intending to. This can break actual games, so fix it up.
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TEST(64, R(reg), R(reg));
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FixupBranch dont_clear_gt = J_CC(CC_NZ);
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BTS(64, R(reg), Imm8(63));
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SetJumpTarget(dont_clear_gt);
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}
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FixupBranch Jit64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set)
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{
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switch (bit)
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@ -255,6 +255,7 @@ protected:
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void FakeLKExit(u32 exit_address_after_return);
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void WriteBLRExit(Arm64Gen::ARM64Reg dest);
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void FixGTBeforeSettingCRFieldBit(Arm64Gen::ARM64Reg reg);
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Arm64Gen::FixupBranch JumpIfCRFieldBit(int field, int bit, bool jump_if_set);
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void ComputeRC0(Arm64Gen::ARM64Reg reg);
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@ -36,6 +36,19 @@ FixupBranch JitArm64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set)
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}
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}
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void JitArm64::FixGTBeforeSettingCRFieldBit(Arm64Gen::ARM64Reg reg)
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{
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// Gross but necessary; if the input is totally zero and we set SO or LT,
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// or even just add the (1<<32), GT will suddenly end up set without us
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// intending to. This can break actual games, so fix it up.
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ARM64Reg WA = gpr.GetReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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ORR(XA, reg, 64 - 63, 0, true); // XB | 1<<63
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CMP(reg, ARM64Reg::ZR);
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CSEL(reg, reg, XA, CC_NEQ);
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gpr.Unlock(WA);
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}
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void JitArm64::mtmsr(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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@ -432,6 +445,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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break;
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case PowerPC::CR_EQ_BIT:
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FixGTBeforeSettingCRFieldBit(XA);
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ORR(XA, XA, 0, 0, true); // XA | 1<<0
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break;
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@ -457,14 +471,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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ARM64Reg XA = gpr.CR(field);
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if (bit != PowerPC::CR_GT_BIT)
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{
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ARM64Reg WB = gpr.GetReg();
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ARM64Reg XB = EncodeRegTo64(WB);
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ORR(XB, XA, 64 - 63, 0, true); // XA | 1<<63
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CMP(XA, ARM64Reg::ZR);
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CSEL(XA, XA, XB, CC_NEQ);
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gpr.Unlock(WB);
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}
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FixGTBeforeSettingCRFieldBit(XA);
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switch (bit)
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{
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@ -569,18 +576,8 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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gpr.BindCRToRegister(field, true);
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XB = gpr.CR(field);
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// Gross but necessary; if the input is totally zero and we set SO or LT,
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// or even just add the (1<<32), GT will suddenly end up set without us
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// intending to. This can break actual games, so fix it up.
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if (bit != PowerPC::CR_GT_BIT)
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{
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ARM64Reg WC = gpr.GetReg();
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ARM64Reg XC = EncodeRegTo64(WC);
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ORR(XC, XB, 64 - 63, 0, true); // XB | 1<<63
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CMP(XB, ARM64Reg::ZR);
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CSEL(XB, XB, XC, CC_NEQ);
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gpr.Unlock(WC);
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}
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FixGTBeforeSettingCRFieldBit(XB);
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switch (bit)
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{
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