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NDSCart: KEY1-gap delays don't apply when the WR bit is set. fixes #377
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@ -1260,8 +1260,14 @@ void WriteROMCnt(u32 val)
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// TODO: advance read position if bit28 is set
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u32 xfercycle = (ROMCnt & (1<<27)) ? 8 : 5;
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u32 cmddelay = 8 + (ROMCnt & 0x1FFF);
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if (datasize) cmddelay += ((ROMCnt >> 16) & 0x3F);
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u32 cmddelay = 8;
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// delays are only applied when the WR bit is cleared
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if (!(ROMCnt & (1<<30)))
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{
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cmddelay += (ROMCnt & 0x1FFF);
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if (datasize) cmddelay += ((ROMCnt >> 16) & 0x3F);
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}
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if (datasize == 0)
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NDS::ScheduleEvent(NDS::Event_ROMTransfer, false, xfercycle*cmddelay, ROMEndTransfer, 0);
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