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DS emulator, sorta
45 Commits 53 Branches 22 Tags 29 MiB
C++ 55.8%
C 42.4%
CMake 0.8%
Assembly 0.6%
Ruby 0.1%
516bc30ee3
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StapleButter 516bc30ee3 * very shitty implementation of save RAM. requires an existing save file for now. 
* refine some SPI code, too. mostly removing a useless function.
* support 16bit accesses to DMAxCNT registers.
2017-01-31 17:34:17 +01:00
.gitignore add more crap 2016-05-16 17:48:40 +02:00
ARM_InstrTable.h uh oh! it's getting further 2017-01-16 04:47:37 +01:00
ARM.cpp * scheduler revamp, simpler design 2017-01-31 03:54:51 +01:00
ARM.h * scheduler revamp, simpler design 2017-01-31 03:54:51 +01:00
ARMInterpreter_ALU.cpp start refactoring shit: more accurate timing and way of counting cycles. 2017-01-30 18:36:11 +01:00
ARMInterpreter_ALU.h start refactoring shit: more accurate timing and way of counting cycles. 2017-01-30 18:36:11 +01:00
ARMInterpreter_Branch.cpp start refactoring shit: more accurate timing and way of counting cycles. 2017-01-30 18:36:11 +01:00
ARMInterpreter_Branch.h start refactoring shit: more accurate timing and way of counting cycles. 2017-01-30 18:36:11 +01:00
ARMInterpreter_LoadStore.cpp * scheduler revamp, simpler design 2017-01-31 03:54:51 +01:00
ARMInterpreter_LoadStore.h start refactoring shit: more accurate timing and way of counting cycles. 2017-01-30 18:36:11 +01:00
ARMInterpreter.cpp start refactoring shit: more accurate timing and way of counting cycles. 2017-01-30 18:36:11 +01:00
ARMInterpreter.h start refactoring shit: more accurate timing and way of counting cycles. 2017-01-30 18:36:11 +01:00
CP15.cpp move TCM shit to CP15.cpp. closer to the real thing (for example now DMA can't access TCM, etc). 2017-01-30 19:11:29 +01:00
CP15.h move TCM shit to CP15.cpp. closer to the real thing (for example now DMA can't access TCM, etc). 2017-01-30 19:11:29 +01:00
DMA.cpp * support for cart secure area 2017-01-23 02:26:05 +01:00
DMA.h DMA support! 2017-01-18 01:33:06 +01:00
FIFO.cpp IPC FIFO emulation. 2017-01-17 01:58:25 +01:00
FIFO.h IPC FIFO emulation. 2017-01-17 01:58:25 +01:00
GPU2D.cpp * fix VRAM address calculation for GPU A 2017-01-31 15:43:22 +01:00
GPU2D.h rotscaled 16color sprites. about fucking time I get this shit working. 2017-01-21 17:06:54 +01:00
GPU.cpp * scheduler revamp, simpler design 2017-01-31 03:54:51 +01:00
GPU.h * start GPU shit: draw BG0 16-color. 2017-01-18 17:57:12 +01:00
main.cpp * scheduler revamp, simpler design 2017-01-31 03:54:51 +01:00
melonDS.cbp esgshdgdfh 2017-01-22 20:37:12 +01:00
melonDS.depend * very shitty implementation of save RAM. requires an existing save file for now. 2017-01-31 17:34:17 +01:00
melonDS.layout hey look, more crap 2016-11-03 01:38:58 +01:00
NDS.cpp * very shitty implementation of save RAM. requires an existing save file for now. 2017-01-31 17:34:17 +01:00
NDS.h * scheduler revamp, simpler design 2017-01-31 03:54:51 +01:00
NDSCart.cpp * very shitty implementation of save RAM. requires an existing save file for now. 2017-01-31 17:34:17 +01:00
NDSCart.h * very shitty implementation of save RAM. requires an existing save file for now. 2017-01-31 17:34:17 +01:00
README.md * somewhat proper event scheduler 2016-12-05 17:08:24 +01:00
RTC.cpp some attempt at cart support 2017-01-22 20:34:59 +01:00
RTC.h * some basic BG display code 2017-01-20 01:18:30 +01:00
SPI.cpp * very shitty implementation of save RAM. requires an existing save file for now. 2017-01-31 17:34:17 +01:00
SPI.h * very shitty implementation of save RAM. requires an existing save file for now. 2017-01-31 17:34:17 +01:00
types.h christ. CodeBlocks is retarded. 2016-12-23 21:22:22 +01:00
Wifi.cpp some more crap emulated. 2016-12-06 17:32:51 +01:00
Wifi.h some more crap emulated. 2016-12-06 17:32:51 +01:00

README.md

melonDS

DS emulator, sorta

the goal is to do things right and fast, akin to blargSNES (but hopefully better)

but also to have fun coding this shit

LOVE MELONS

NO ASKING ROMZ!! ILLEGAL

license will eventually be GPL or some crap. don't steal the code and make money off of it or claim it as your own or be an asshole.

TODO LIST

  • take code fetch waitstates into account when fetching instructions, and during branches (pipeline shit) (tricky, some code fetches are nonsequential)