2017-01-22 12:34:59 -07:00
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/*
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2018-10-17 16:54:21 -06:00
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Copyright 2016-2017 StapleButter
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2017-01-22 12:34:59 -07:00
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This file is part of melonDS.
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melonDS is free software: you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation, either version 3 of the License, or (at your option)
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any later version.
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melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#include <stdio.h>
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#include <string.h>
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#include "NDS.h"
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#include "NDSCart.h"
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2017-06-25 09:35:45 -06:00
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#include "ARM.h"
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2018-12-11 11:16:19 -07:00
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#include "CRC32.h"
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2017-01-22 12:34:59 -07:00
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2017-10-10 16:32:43 -06:00
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#include "melon_fopen.h"
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2017-01-31 09:34:17 -07:00
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namespace NDSCart_SRAM
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{
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u8* SRAM;
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u32 SRAMLength;
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2018-10-23 14:54:09 -06:00
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char SRAMPath[1024];
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2017-02-03 08:57:31 -07:00
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void (*WriteFunc)(u8 val, bool islast);
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2017-01-31 09:34:17 -07:00
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u32 Hold;
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u8 CurCmd;
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u32 DataPos;
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u8 Data;
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u8 StatusReg;
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u32 Addr;
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2017-02-03 08:57:31 -07:00
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void Write_Null(u8 val, bool islast);
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void Write_EEPROMTiny(u8 val, bool islast);
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void Write_EEPROM(u8 val, bool islast);
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void Write_Flash(u8 val, bool islast);
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void Write_Discover(u8 val, bool islast);
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2017-02-07 14:23:46 -07:00
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bool Init()
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2017-01-31 09:34:17 -07:00
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{
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SRAM = NULL;
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2017-02-07 14:23:46 -07:00
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return true;
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}
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void DeInit()
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{
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if (SRAM) delete[] SRAM;
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2017-01-31 09:34:17 -07:00
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}
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void Reset()
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2017-02-03 08:57:31 -07:00
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{
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2017-03-29 10:59:20 -06:00
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if (SRAM) delete[] SRAM;
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SRAM = NULL;
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2017-02-03 08:57:31 -07:00
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}
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2018-10-17 16:54:21 -06:00
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void DoSavestate(Savestate* file)
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{
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file->Section("NDCS");
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2018-12-11 12:39:07 -07:00
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// we reload the SRAM contents.
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2018-10-17 16:54:21 -06:00
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// it should be the same file (as it should be the same ROM, duh)
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// but the contents may change
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// TODO maybe: possibility to save to a separate file when using savestates????
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// also the SRAM size shouldn't change. unless something something autodetect something but fuck that code.
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//if (!file->Saving && SRAMLength)
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// delete[] SRAM;
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u32 oldlen = SRAMLength;
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file->Var32(&SRAMLength);
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if (SRAMLength != oldlen)
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{
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printf("savestate: VERY BAD!!!! SRAM LENGTH DIFFERENT. %d -> %d\n", oldlen, SRAMLength);
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printf("oh well. loading it anyway. adsfgdsf\n");
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if (oldlen) delete[] SRAM;
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if (SRAMLength) SRAM = new u8[SRAMLength];
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}
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if (SRAMLength)
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{
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//if (!file->Saving)
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// SRAM = new u8[SRAMLength];
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file->VarArray(SRAM, SRAMLength);
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}
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// SPI status shito
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file->Var32(&Hold);
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file->Var8(&CurCmd);
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file->Var32(&DataPos);
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file->Var8(&Data);
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file->Var8(&StatusReg);
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file->Var32(&Addr);
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}
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2018-12-11 12:39:07 -07:00
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void LoadSave(const char* path, u32 type)
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2017-01-31 09:34:17 -07:00
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{
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if (SRAM) delete[] SRAM;
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2017-02-07 14:23:46 -07:00
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2018-10-23 14:54:09 -06:00
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strncpy(SRAMPath, path, 1023);
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SRAMPath[1023] = '\0';
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2017-02-03 08:57:31 -07:00
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2017-10-10 16:32:43 -06:00
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FILE* f = melon_fopen(path, "rb");
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2017-01-31 09:34:17 -07:00
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if (f)
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{
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fseek(f, 0, SEEK_END);
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SRAMLength = (u32)ftell(f);
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SRAM = new u8[SRAMLength];
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fseek(f, 0, SEEK_SET);
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fread(SRAM, SRAMLength, 1, f);
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fclose(f);
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2018-12-11 12:39:07 -07:00
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}
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else
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{
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2018-12-11 19:18:14 -07:00
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if (type > 8) type = 0;
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2018-12-11 12:39:07 -07:00
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int sramlen[] = {0, 512, 8192, 65536, 256*1024, 512*1024, 1024*1024, 8192*1024, 32768*1024};
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SRAMLength = sramlen[type];
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2017-01-31 09:34:17 -07:00
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2018-12-11 12:39:07 -07:00
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if (SRAMLength)
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2017-01-31 09:34:17 -07:00
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{
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2018-12-11 12:39:07 -07:00
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SRAM = new u8[SRAMLength];
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2018-12-30 12:57:20 -07:00
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memset(SRAM, 0xFF, SRAMLength);
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2017-01-31 09:34:17 -07:00
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}
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}
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2018-12-11 12:39:07 -07:00
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switch (SRAMLength)
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2017-01-31 09:34:17 -07:00
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{
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2018-12-11 12:39:07 -07:00
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case 512: WriteFunc = Write_EEPROMTiny; break;
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case 8192:
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case 65536: WriteFunc = Write_EEPROM; break;
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case 256*1024:
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case 512*1024:
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case 1024*1024:
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2018-12-12 12:59:08 -07:00
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case 8192*1024: WriteFunc = Write_Flash; break;
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case 32768*1024: WriteFunc = Write_Null; break; // NAND FLASH, handled differently
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2018-12-11 12:39:07 -07:00
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default:
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printf("!! BAD SAVE LENGTH %d\n", SRAMLength);
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case 0:
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WriteFunc = Write_Null;
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break;
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2017-01-31 09:34:17 -07:00
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}
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Hold = 0;
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CurCmd = 0;
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Data = 0;
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StatusReg = 0x00;
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}
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2018-10-23 16:24:36 -06:00
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void RelocateSave(const char* path, bool write)
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2018-10-23 14:54:09 -06:00
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{
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2018-10-23 16:24:36 -06:00
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if (!write)
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{
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2018-12-11 12:39:07 -07:00
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LoadSave(path, 0); // lazy
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2018-10-23 16:24:36 -06:00
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return;
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}
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2018-10-23 14:54:09 -06:00
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strncpy(SRAMPath, path, 1023);
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SRAMPath[1023] = '\0';
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FILE* f = melon_fopen(path, "wb");
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if (!f)
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{
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printf("NDSCart_SRAM::RelocateSave: failed to create new file. fuck\n");
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return;
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}
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fwrite(SRAM, SRAMLength, 1, f);
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fclose(f);
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}
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2017-01-31 09:34:17 -07:00
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u8 Read()
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{
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return Data;
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}
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2017-02-03 08:57:31 -07:00
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void Write_Null(u8 val, bool islast) {}
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void Write_EEPROMTiny(u8 val, bool islast)
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{
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2017-03-23 16:47:55 -06:00
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switch (CurCmd)
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{
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case 0x02:
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case 0x0A:
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if (DataPos < 1)
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{
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Addr = val;
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Data = 0;
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}
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else
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{
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2017-04-10 17:21:35 -06:00
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SRAM[(Addr + ((CurCmd==0x0A)?0x100:0)) & 0x1FF] = val;
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2017-03-23 16:47:55 -06:00
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Addr++;
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}
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break;
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case 0x03:
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case 0x0B:
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if (DataPos < 1)
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{
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Addr = val;
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Data = 0;
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}
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else
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{
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2017-04-10 17:21:35 -06:00
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Data = SRAM[(Addr + ((CurCmd==0x0B)?0x100:0)) & 0x1FF];
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2017-03-23 16:47:55 -06:00
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Addr++;
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}
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break;
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case 0x9F:
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Data = 0xFF;
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break;
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default:
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if (DataPos==0)
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printf("unknown tiny EEPROM save command %02X\n", CurCmd);
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break;
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}
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2017-02-03 08:57:31 -07:00
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}
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void Write_EEPROM(u8 val, bool islast)
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{
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switch (CurCmd)
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{
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case 0x02:
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if (DataPos < 2)
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{
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Addr <<= 8;
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Addr |= val;
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Data = 0;
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}
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else
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{
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2017-02-05 09:45:17 -07:00
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SRAM[Addr & (SRAMLength-1)] = val;
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2017-02-03 08:57:31 -07:00
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Addr++;
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}
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break;
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case 0x03:
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if (DataPos < 2)
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{
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Addr <<= 8;
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Addr |= val;
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Data = 0;
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}
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else
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{
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2017-02-05 09:45:17 -07:00
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Data = SRAM[Addr & (SRAMLength-1)];
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2017-02-03 08:57:31 -07:00
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Addr++;
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}
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break;
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case 0x9F:
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Data = 0xFF;
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break;
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default:
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if (DataPos==0)
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printf("unknown EEPROM save command %02X\n", CurCmd);
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break;
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}
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}
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void Write_Flash(u8 val, bool islast)
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{
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switch (CurCmd)
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{
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2017-03-29 14:12:53 -06:00
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case 0x02:
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if (DataPos < 3)
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{
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Addr <<= 8;
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Addr |= val;
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Data = 0;
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}
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else
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{
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SRAM[Addr & (SRAMLength-1)] = 0;
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Addr++;
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}
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break;
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2017-02-03 08:57:31 -07:00
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case 0x03:
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if (DataPos < 3)
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{
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Addr <<= 8;
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Addr |= val;
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Data = 0;
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}
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else
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{
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2017-03-23 16:55:22 -06:00
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Data = SRAM[Addr & (SRAMLength-1)];
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2017-02-03 08:57:31 -07:00
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Addr++;
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}
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break;
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case 0x0A:
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if (DataPos < 3)
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{
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Addr <<= 8;
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Addr |= val;
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Data = 0;
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}
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else
|
|
|
|
|
{
|
2017-03-23 16:55:22 -06:00
|
|
|
|
SRAM[Addr & (SRAMLength-1)] = val;
|
2017-02-03 08:57:31 -07:00
|
|
|
|
Addr++;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x9F:
|
|
|
|
|
Data = 0xFF;
|
|
|
|
|
break;
|
|
|
|
|
|
2017-03-29 14:12:53 -06:00
|
|
|
|
case 0xD8:
|
|
|
|
|
if (DataPos < 3)
|
|
|
|
|
{
|
|
|
|
|
Addr <<= 8;
|
|
|
|
|
Addr |= val;
|
|
|
|
|
Data = 0;
|
|
|
|
|
}
|
|
|
|
|
if (DataPos == 2)
|
|
|
|
|
{
|
|
|
|
|
for (u32 i = 0; i < 0x10000; i++)
|
|
|
|
|
{
|
|
|
|
|
SRAM[Addr & (SRAMLength-1)] = 0;
|
|
|
|
|
Addr++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xDB:
|
|
|
|
|
if (DataPos < 3)
|
|
|
|
|
{
|
|
|
|
|
Addr <<= 8;
|
|
|
|
|
Addr |= val;
|
|
|
|
|
Data = 0;
|
|
|
|
|
}
|
|
|
|
|
if (DataPos == 2)
|
|
|
|
|
{
|
|
|
|
|
for (u32 i = 0; i < 0x100; i++)
|
|
|
|
|
{
|
|
|
|
|
SRAM[Addr & (SRAMLength-1)] = 0;
|
|
|
|
|
Addr++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
2017-02-03 08:57:31 -07:00
|
|
|
|
default:
|
|
|
|
|
if (DataPos==0)
|
|
|
|
|
printf("unknown Flash save command %02X\n", CurCmd);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-31 09:34:17 -07:00
|
|
|
|
void Write(u8 val, u32 hold)
|
|
|
|
|
{
|
2017-02-03 08:57:31 -07:00
|
|
|
|
bool islast = false;
|
|
|
|
|
|
2017-01-31 09:34:17 -07:00
|
|
|
|
if (!hold)
|
|
|
|
|
{
|
2017-02-03 08:57:31 -07:00
|
|
|
|
if (Hold) islast = true;
|
2017-06-25 16:38:07 -06:00
|
|
|
|
else CurCmd = val;
|
2017-01-31 09:34:17 -07:00
|
|
|
|
Hold = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (hold && (!Hold))
|
|
|
|
|
{
|
|
|
|
|
CurCmd = val;
|
|
|
|
|
Hold = 1;
|
|
|
|
|
Data = 0;
|
2017-02-03 08:57:31 -07:00
|
|
|
|
DataPos = 0;
|
2017-01-31 09:34:17 -07:00
|
|
|
|
Addr = 0;
|
|
|
|
|
//printf("save SPI command %02X\n", CurCmd);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (CurCmd)
|
|
|
|
|
{
|
2017-04-10 12:56:22 -06:00
|
|
|
|
case 0x00:
|
|
|
|
|
// Pok<6F>mon carts have an IR transceiver thing, and send this
|
|
|
|
|
// to bypass it and access SRAM.
|
|
|
|
|
// TODO: design better
|
|
|
|
|
CurCmd = val;
|
|
|
|
|
break;
|
2017-07-15 11:34:35 -06:00
|
|
|
|
case 0x08:
|
|
|
|
|
// see above
|
|
|
|
|
// TODO: work out how the IR thing works. emulate it.
|
|
|
|
|
Data = 0xAA;
|
|
|
|
|
break;
|
2017-04-10 12:56:22 -06:00
|
|
|
|
|
2017-02-03 08:57:31 -07:00
|
|
|
|
case 0x02:
|
|
|
|
|
case 0x03:
|
|
|
|
|
case 0x0A:
|
|
|
|
|
case 0x0B:
|
|
|
|
|
case 0x9F:
|
2017-04-25 08:24:31 -06:00
|
|
|
|
case 0xD8:
|
|
|
|
|
case 0xDB:
|
2017-02-03 08:57:31 -07:00
|
|
|
|
WriteFunc(val, islast);
|
|
|
|
|
DataPos++;
|
2017-01-31 09:34:17 -07:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x04: // write disable
|
|
|
|
|
StatusReg &= ~(1<<1);
|
|
|
|
|
Data = 0;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x05: // read status reg
|
|
|
|
|
Data = StatusReg;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x06: // write enable
|
|
|
|
|
StatusReg |= (1<<1);
|
|
|
|
|
Data = 0;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
2017-04-10 12:56:22 -06:00
|
|
|
|
if (DataPos==0)
|
2017-08-16 14:20:53 -06:00
|
|
|
|
printf("unknown save SPI command %02X %02X %d\n", CurCmd, val, islast);
|
2017-01-31 09:34:17 -07:00
|
|
|
|
break;
|
|
|
|
|
}
|
2017-02-03 08:57:31 -07:00
|
|
|
|
|
2017-03-23 16:55:22 -06:00
|
|
|
|
if (islast && (CurCmd == 0x02 || CurCmd == 0x0A) && (SRAMLength > 0))
|
2017-02-03 08:57:31 -07:00
|
|
|
|
{
|
2017-10-10 16:32:43 -06:00
|
|
|
|
FILE* f = melon_fopen(SRAMPath, "wb");
|
2017-02-03 08:57:31 -07:00
|
|
|
|
if (f)
|
|
|
|
|
{
|
|
|
|
|
fwrite(SRAM, SRAMLength, 1, f);
|
|
|
|
|
fclose(f);
|
|
|
|
|
}
|
|
|
|
|
}
|
2017-01-31 09:34:17 -07:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
namespace NDSCart
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
u16 SPICnt;
|
|
|
|
|
u32 ROMCnt;
|
|
|
|
|
|
|
|
|
|
u8 ROMCommand[8];
|
|
|
|
|
u32 ROMDataOut;
|
|
|
|
|
|
|
|
|
|
u8 DataOut[0x4000];
|
|
|
|
|
u32 DataOutPos;
|
|
|
|
|
u32 DataOutLen;
|
|
|
|
|
|
|
|
|
|
bool CartInserted;
|
|
|
|
|
u8* CartROM;
|
|
|
|
|
u32 CartROMSize;
|
2018-12-11 11:16:19 -07:00
|
|
|
|
u32 CartCRC;
|
2017-01-22 12:34:59 -07:00
|
|
|
|
u32 CartID;
|
2017-01-22 18:26:05 -07:00
|
|
|
|
bool CartIsHomebrew;
|
2017-01-22 12:34:59 -07:00
|
|
|
|
|
|
|
|
|
u32 CmdEncMode;
|
|
|
|
|
u32 DataEncMode;
|
|
|
|
|
|
|
|
|
|
u32 Key1_KeyBuf[0x412];
|
|
|
|
|
|
|
|
|
|
u64 Key2_X;
|
|
|
|
|
u64 Key2_Y;
|
|
|
|
|
|
|
|
|
|
|
2018-12-12 12:59:08 -07:00
|
|
|
|
void ROMCommand_Retail(u8* cmd);
|
|
|
|
|
void ROMCommand_RetailNAND(u8* cmd);
|
|
|
|
|
|
|
|
|
|
void (*ROMCommandHandler)(u8* cmd);
|
|
|
|
|
|
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
u32 ByteSwap(u32 val)
|
|
|
|
|
{
|
|
|
|
|
return (val >> 24) | ((val >> 8) & 0xFF00) | ((val << 8) & 0xFF0000) | (val << 24);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void Key1_Encrypt(u32* data)
|
|
|
|
|
{
|
|
|
|
|
u32 y = data[0];
|
|
|
|
|
u32 x = data[1];
|
|
|
|
|
u32 z;
|
|
|
|
|
|
|
|
|
|
for (u32 i = 0x0; i <= 0xF; i++)
|
|
|
|
|
{
|
|
|
|
|
z = Key1_KeyBuf[i] ^ x;
|
|
|
|
|
x = Key1_KeyBuf[0x012 + (z >> 24) ];
|
|
|
|
|
x += Key1_KeyBuf[0x112 + ((z >> 16) & 0xFF)];
|
|
|
|
|
x ^= Key1_KeyBuf[0x212 + ((z >> 8) & 0xFF)];
|
|
|
|
|
x += Key1_KeyBuf[0x312 + (z & 0xFF)];
|
|
|
|
|
x ^= y;
|
|
|
|
|
y = z;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
data[0] = x ^ Key1_KeyBuf[0x10];
|
|
|
|
|
data[1] = y ^ Key1_KeyBuf[0x11];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void Key1_Decrypt(u32* data)
|
|
|
|
|
{
|
|
|
|
|
u32 y = data[0];
|
|
|
|
|
u32 x = data[1];
|
|
|
|
|
u32 z;
|
|
|
|
|
|
|
|
|
|
for (u32 i = 0x11; i >= 0x2; i--)
|
|
|
|
|
{
|
|
|
|
|
z = Key1_KeyBuf[i] ^ x;
|
|
|
|
|
x = Key1_KeyBuf[0x012 + (z >> 24) ];
|
|
|
|
|
x += Key1_KeyBuf[0x112 + ((z >> 16) & 0xFF)];
|
|
|
|
|
x ^= Key1_KeyBuf[0x212 + ((z >> 8) & 0xFF)];
|
|
|
|
|
x += Key1_KeyBuf[0x312 + (z & 0xFF)];
|
|
|
|
|
x ^= y;
|
|
|
|
|
y = z;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
data[0] = x ^ Key1_KeyBuf[0x1];
|
|
|
|
|
data[1] = y ^ Key1_KeyBuf[0x0];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void Key1_ApplyKeycode(u32* keycode, u32 mod)
|
|
|
|
|
{
|
|
|
|
|
Key1_Encrypt(&keycode[1]);
|
|
|
|
|
Key1_Encrypt(&keycode[0]);
|
|
|
|
|
|
|
|
|
|
u32 temp[2] = {0,0};
|
|
|
|
|
|
|
|
|
|
for (u32 i = 0; i <= 0x11; i++)
|
|
|
|
|
{
|
|
|
|
|
Key1_KeyBuf[i] ^= ByteSwap(keycode[i % mod]);
|
|
|
|
|
}
|
|
|
|
|
for (u32 i = 0; i <= 0x410; i+=2)
|
|
|
|
|
{
|
|
|
|
|
Key1_Encrypt(temp);
|
|
|
|
|
Key1_KeyBuf[i ] = temp[1];
|
|
|
|
|
Key1_KeyBuf[i+1] = temp[0];
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void Key1_InitKeycode(u32 idcode, u32 level, u32 mod)
|
|
|
|
|
{
|
|
|
|
|
memcpy(Key1_KeyBuf, &NDS::ARM7BIOS[0x30], 0x1048); // hax
|
|
|
|
|
|
|
|
|
|
u32 keycode[3] = {idcode, idcode>>1, idcode<<1};
|
|
|
|
|
if (level >= 1) Key1_ApplyKeycode(keycode, mod);
|
|
|
|
|
if (level >= 2) Key1_ApplyKeycode(keycode, mod);
|
|
|
|
|
if (level >= 3)
|
|
|
|
|
{
|
|
|
|
|
keycode[1] <<= 1;
|
|
|
|
|
keycode[2] >>= 1;
|
|
|
|
|
Key1_ApplyKeycode(keycode, mod);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
void Key2_Encrypt(u8* data, u32 len)
|
|
|
|
|
{
|
|
|
|
|
for (u32 i = 0; i < len; i++)
|
|
|
|
|
{
|
|
|
|
|
Key2_X = (((Key2_X >> 5) ^
|
|
|
|
|
(Key2_X >> 17) ^
|
|
|
|
|
(Key2_X >> 18) ^
|
|
|
|
|
(Key2_X >> 31)) & 0xFF)
|
|
|
|
|
+ (Key2_X << 8);
|
|
|
|
|
Key2_Y = (((Key2_Y >> 5) ^
|
|
|
|
|
(Key2_Y >> 23) ^
|
|
|
|
|
(Key2_Y >> 18) ^
|
|
|
|
|
(Key2_Y >> 31)) & 0xFF)
|
|
|
|
|
+ (Key2_Y << 8);
|
|
|
|
|
|
|
|
|
|
Key2_X &= 0x0000007FFFFFFFFFULL;
|
|
|
|
|
Key2_Y &= 0x0000007FFFFFFFFFULL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2017-02-07 14:23:46 -07:00
|
|
|
|
bool Init()
|
|
|
|
|
{
|
|
|
|
|
if (!NDSCart_SRAM::Init()) return false;
|
|
|
|
|
|
2017-03-20 10:39:42 -06:00
|
|
|
|
CartROM = NULL;
|
|
|
|
|
|
2017-02-07 14:23:46 -07:00
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void DeInit()
|
2017-01-22 12:34:59 -07:00
|
|
|
|
{
|
2017-03-20 10:39:42 -06:00
|
|
|
|
if (CartROM) delete[] CartROM;
|
|
|
|
|
|
2017-02-07 14:23:46 -07:00
|
|
|
|
NDSCart_SRAM::DeInit();
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void Reset()
|
|
|
|
|
{
|
|
|
|
|
SPICnt = 0;
|
|
|
|
|
ROMCnt = 0;
|
|
|
|
|
|
|
|
|
|
memset(ROMCommand, 0, 8);
|
|
|
|
|
ROMDataOut = 0;
|
|
|
|
|
|
|
|
|
|
Key2_X = 0;
|
|
|
|
|
Key2_Y = 0;
|
|
|
|
|
|
|
|
|
|
memset(DataOut, 0, 0x4000);
|
|
|
|
|
DataOutPos = 0;
|
|
|
|
|
DataOutLen = 0;
|
|
|
|
|
|
|
|
|
|
CartInserted = false;
|
2017-03-29 10:59:20 -06:00
|
|
|
|
if (CartROM) delete[] CartROM;
|
2017-01-22 12:34:59 -07:00
|
|
|
|
CartROM = NULL;
|
|
|
|
|
CartROMSize = 0;
|
|
|
|
|
CartID = 0;
|
2017-01-22 18:26:05 -07:00
|
|
|
|
CartIsHomebrew = false;
|
2017-01-22 12:34:59 -07:00
|
|
|
|
|
2018-12-12 12:59:08 -07:00
|
|
|
|
ROMCommandHandler = NULL;
|
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
CmdEncMode = 0;
|
|
|
|
|
DataEncMode = 0;
|
2017-01-31 09:34:17 -07:00
|
|
|
|
|
|
|
|
|
NDSCart_SRAM::Reset();
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|
|
|
|
|
|
2018-10-17 16:54:21 -06:00
|
|
|
|
void DoSavestate(Savestate* file)
|
|
|
|
|
{
|
|
|
|
|
file->Section("NDSC");
|
|
|
|
|
|
|
|
|
|
file->Var16(&SPICnt);
|
|
|
|
|
file->Var32(&ROMCnt);
|
|
|
|
|
|
|
|
|
|
file->VarArray(ROMCommand, 8);
|
|
|
|
|
file->Var32(&ROMDataOut);
|
|
|
|
|
|
|
|
|
|
file->VarArray(DataOut, 0x4000);
|
|
|
|
|
file->Var32(&DataOutPos);
|
|
|
|
|
file->Var32(&DataOutLen);
|
|
|
|
|
|
|
|
|
|
// cart inserted/len/ROM/etc should be already populated
|
|
|
|
|
// savestate should be loaded after the right game is loaded
|
|
|
|
|
// (TODO: system to verify that indeed the right ROM is loaded)
|
|
|
|
|
// (what to CRC? whole ROM? code binaries? latter would be more convenient for ie. romhaxing)
|
|
|
|
|
|
|
|
|
|
file->Var32(&CmdEncMode);
|
|
|
|
|
file->Var32(&DataEncMode);
|
|
|
|
|
|
|
|
|
|
// TODO: check KEY1 shit??
|
|
|
|
|
|
|
|
|
|
NDSCart_SRAM::DoSavestate(file);
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
|
2018-04-26 16:17:05 -06:00
|
|
|
|
void ApplyDLDIPatch()
|
|
|
|
|
{
|
|
|
|
|
// TODO: embed patches? let the user choose? default to some builtin driver?
|
|
|
|
|
|
|
|
|
|
u32 offset = *(u32*)&CartROM[0x20];
|
|
|
|
|
u32 size = *(u32*)&CartROM[0x2C];
|
|
|
|
|
|
|
|
|
|
u8* binary = &CartROM[offset];
|
|
|
|
|
u32 dldioffset = 0;
|
|
|
|
|
|
|
|
|
|
for (u32 i = 0; i < size; i++)
|
|
|
|
|
{
|
|
|
|
|
if (*(u32*)&binary[i ] == 0xBF8DA5ED &&
|
|
|
|
|
*(u32*)&binary[i+4] == 0x69684320 &&
|
|
|
|
|
*(u32*)&binary[i+8] == 0x006D6873)
|
|
|
|
|
{
|
|
|
|
|
dldioffset = i;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!dldioffset)
|
|
|
|
|
{
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
printf("DLDI shit found at %08X (%08X)\n", dldioffset, offset+dldioffset);
|
|
|
|
|
|
|
|
|
|
FILE* f = fopen("dldi.bin", "rb");
|
|
|
|
|
if (!f)
|
|
|
|
|
{
|
|
|
|
|
printf("no DLDI patch available. oh well\n");
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
u32 dldisize;
|
|
|
|
|
fseek(f, 0, SEEK_END);
|
|
|
|
|
dldisize = ftell(f);
|
|
|
|
|
fseek(f, 0, SEEK_SET);
|
|
|
|
|
|
|
|
|
|
u8* patch = new u8[dldisize];
|
|
|
|
|
fread(patch, dldisize, 1, f);
|
|
|
|
|
fclose(f);
|
|
|
|
|
|
|
|
|
|
if (*(u32*)&patch[0] != 0xBF8DA5ED ||
|
|
|
|
|
*(u32*)&patch[4] != 0x69684320 ||
|
|
|
|
|
*(u32*)&patch[8] != 0x006D6873)
|
|
|
|
|
{
|
|
|
|
|
printf("bad DLDI patch\n");
|
|
|
|
|
delete[] patch;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (patch[0x0D] > binary[dldioffset+0x0F])
|
|
|
|
|
{
|
|
|
|
|
printf("DLDI driver ain't gonna fit, sorry\n");
|
|
|
|
|
delete[] patch;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
printf("existing driver is: %s\n", &binary[dldioffset+0x10]);
|
|
|
|
|
printf("new driver is: %s\n", &patch[0x10]);
|
|
|
|
|
|
|
|
|
|
u32 memaddr = *(u32*)&binary[dldioffset+0x40];
|
|
|
|
|
if (memaddr == 0)
|
|
|
|
|
memaddr = *(u32*)&binary[dldioffset+0x68] - 0x80;
|
|
|
|
|
|
|
|
|
|
u32 patchbase = *(u32*)&patch[0x40];
|
|
|
|
|
u32 delta = memaddr - patchbase;
|
|
|
|
|
|
|
|
|
|
u32 patchsize = 1 << patch[0x0D];
|
|
|
|
|
u32 patchend = patchbase + patchsize;
|
|
|
|
|
|
|
|
|
|
memcpy(&binary[dldioffset], patch, dldisize);
|
|
|
|
|
|
|
|
|
|
*(u32*)&binary[dldioffset+0x40] += delta;
|
|
|
|
|
*(u32*)&binary[dldioffset+0x44] += delta;
|
|
|
|
|
*(u32*)&binary[dldioffset+0x48] += delta;
|
|
|
|
|
*(u32*)&binary[dldioffset+0x4C] += delta;
|
|
|
|
|
*(u32*)&binary[dldioffset+0x50] += delta;
|
|
|
|
|
*(u32*)&binary[dldioffset+0x54] += delta;
|
|
|
|
|
*(u32*)&binary[dldioffset+0x58] += delta;
|
|
|
|
|
*(u32*)&binary[dldioffset+0x5C] += delta;
|
|
|
|
|
|
|
|
|
|
*(u32*)&binary[dldioffset+0x68] += delta;
|
|
|
|
|
*(u32*)&binary[dldioffset+0x6C] += delta;
|
|
|
|
|
*(u32*)&binary[dldioffset+0x70] += delta;
|
|
|
|
|
*(u32*)&binary[dldioffset+0x74] += delta;
|
|
|
|
|
*(u32*)&binary[dldioffset+0x78] += delta;
|
|
|
|
|
*(u32*)&binary[dldioffset+0x7C] += delta;
|
|
|
|
|
|
|
|
|
|
u8 fixmask = patch[0x0E];
|
|
|
|
|
|
|
|
|
|
if (fixmask & 0x01)
|
|
|
|
|
{
|
|
|
|
|
u32 fixstart = *(u32*)&patch[0x40] - patchbase;
|
|
|
|
|
u32 fixend = *(u32*)&patch[0x44] - patchbase;
|
|
|
|
|
|
|
|
|
|
for (u32 addr = fixstart; addr < fixend; addr+=4)
|
|
|
|
|
{
|
|
|
|
|
u32 val = *(u32*)&binary[dldioffset+addr];
|
|
|
|
|
if (val >= patchbase && val < patchend)
|
|
|
|
|
*(u32*)&binary[dldioffset+addr] += delta;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (fixmask & 0x02)
|
|
|
|
|
{
|
|
|
|
|
u32 fixstart = *(u32*)&patch[0x48] - patchbase;
|
|
|
|
|
u32 fixend = *(u32*)&patch[0x4C] - patchbase;
|
|
|
|
|
|
|
|
|
|
for (u32 addr = fixstart; addr < fixend; addr+=4)
|
|
|
|
|
{
|
|
|
|
|
u32 val = *(u32*)&binary[dldioffset+addr];
|
|
|
|
|
if (val >= patchbase && val < patchend)
|
|
|
|
|
*(u32*)&binary[dldioffset+addr] += delta;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (fixmask & 0x04)
|
|
|
|
|
{
|
|
|
|
|
u32 fixstart = *(u32*)&patch[0x50] - patchbase;
|
|
|
|
|
u32 fixend = *(u32*)&patch[0x54] - patchbase;
|
|
|
|
|
|
|
|
|
|
for (u32 addr = fixstart; addr < fixend; addr+=4)
|
|
|
|
|
{
|
|
|
|
|
u32 val = *(u32*)&binary[dldioffset+addr];
|
|
|
|
|
if (val >= patchbase && val < patchend)
|
|
|
|
|
*(u32*)&binary[dldioffset+addr] += delta;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (fixmask & 0x08)
|
|
|
|
|
{
|
|
|
|
|
u32 fixstart = *(u32*)&patch[0x58] - patchbase;
|
|
|
|
|
u32 fixend = *(u32*)&patch[0x5C] - patchbase;
|
|
|
|
|
|
|
|
|
|
memset(&binary[dldioffset+fixstart], 0, fixend-fixstart);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
delete[] patch;
|
|
|
|
|
printf("applied DLDI patch\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2018-12-11 11:47:03 -07:00
|
|
|
|
bool ReadROMParams(u32* params)
|
|
|
|
|
{
|
|
|
|
|
// format for romlist.bin:
|
|
|
|
|
// [CRC32] [ROM size] [save type] [reserved]
|
|
|
|
|
// list must be sorted by CRC
|
|
|
|
|
|
2018-12-11 13:52:21 -07:00
|
|
|
|
FILE* f = melon_fopen_local("romlist.bin", "rb");
|
2018-12-11 11:47:03 -07:00
|
|
|
|
if (!f) return false;
|
|
|
|
|
|
|
|
|
|
fseek(f, 0, SEEK_END);
|
|
|
|
|
u32 len = (u32)ftell(f);
|
|
|
|
|
u32 maxlen = len;
|
|
|
|
|
len >>= 4; // 16 bytes per entry
|
|
|
|
|
|
|
|
|
|
u32 offset = 0;
|
|
|
|
|
u32 chk_size = len >> 1;
|
|
|
|
|
for (;;)
|
|
|
|
|
{
|
|
|
|
|
u32 crc = 0;
|
|
|
|
|
fseek(f, offset + (chk_size << 4), SEEK_SET);
|
|
|
|
|
fread(&crc, 4, 1, f);
|
|
|
|
|
|
|
|
|
|
printf("chk_size=%d, crc=%08X, wanted=%08X, offset=%08X\n", chk_size, crc, CartCRC, offset);
|
|
|
|
|
|
|
|
|
|
if (crc == CartCRC)
|
|
|
|
|
{
|
|
|
|
|
fread(params, 4, 3, f);
|
|
|
|
|
fclose(f);
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (crc < CartCRC)
|
|
|
|
|
{
|
|
|
|
|
if (chk_size == 0)
|
|
|
|
|
offset += 0x10;
|
|
|
|
|
else
|
|
|
|
|
offset += (chk_size << 4);
|
|
|
|
|
}
|
|
|
|
|
else if (chk_size == 0)
|
|
|
|
|
{
|
|
|
|
|
fclose(f);
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
chk_size >>= 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (offset >= maxlen)
|
|
|
|
|
{
|
|
|
|
|
fclose(f);
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2018-10-23 13:52:41 -06:00
|
|
|
|
bool LoadROM(const char* path, const char* sram, bool direct)
|
2017-01-22 12:34:59 -07:00
|
|
|
|
{
|
|
|
|
|
// TODO: streaming mode? for really big ROMs or systems with limited RAM
|
|
|
|
|
// for now we're lazy
|
|
|
|
|
|
2017-10-10 16:32:43 -06:00
|
|
|
|
FILE* f = melon_fopen(path, "rb");
|
2017-02-07 15:31:21 -07:00
|
|
|
|
if (!f)
|
|
|
|
|
{
|
|
|
|
|
return false;
|
|
|
|
|
}
|
2017-01-22 12:34:59 -07:00
|
|
|
|
|
2017-10-10 16:01:05 -06:00
|
|
|
|
NDS::Reset();
|
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
fseek(f, 0, SEEK_END);
|
|
|
|
|
u32 len = (u32)ftell(f);
|
|
|
|
|
|
|
|
|
|
CartROMSize = 0x200;
|
|
|
|
|
while (CartROMSize < len)
|
|
|
|
|
CartROMSize <<= 1;
|
|
|
|
|
|
|
|
|
|
u32 gamecode;
|
|
|
|
|
fseek(f, 0x0C, SEEK_SET);
|
|
|
|
|
fread(&gamecode, 4, 1, f);
|
|
|
|
|
|
|
|
|
|
CartROM = new u8[CartROMSize];
|
|
|
|
|
memset(CartROM, 0, CartROMSize);
|
|
|
|
|
fseek(f, 0, SEEK_SET);
|
|
|
|
|
fread(CartROM, 1, len, f);
|
|
|
|
|
|
|
|
|
|
fclose(f);
|
|
|
|
|
//CartROM = f;
|
|
|
|
|
|
2018-12-11 11:16:19 -07:00
|
|
|
|
CartCRC = CRC32(CartROM, CartROMSize);
|
|
|
|
|
printf("ROM CRC32: %08X\n", CartCRC);
|
|
|
|
|
|
2018-12-11 11:47:03 -07:00
|
|
|
|
u32 romparams[3];
|
|
|
|
|
if (!ReadROMParams(romparams))
|
|
|
|
|
{
|
|
|
|
|
// set defaults
|
|
|
|
|
printf("ROM entry not found\n");
|
2018-12-11 12:39:07 -07:00
|
|
|
|
|
|
|
|
|
romparams[0] = CartROMSize;
|
|
|
|
|
if (*(u32*)&CartROM[0x20] < 0x4000)
|
|
|
|
|
romparams[1] = 0; // no saveRAM for homebrew
|
|
|
|
|
else
|
|
|
|
|
romparams[1] = 2; // assume EEPROM 64k (TODO FIXME)
|
2018-12-11 11:47:03 -07:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
printf("ROM entry: %08X %08X %08X\n", romparams[0], romparams[1], romparams[2]);
|
|
|
|
|
|
2018-12-12 12:59:08 -07:00
|
|
|
|
if (romparams[0] != len) printf("!! bad ROM size %d (expected %d) rounded to %d\n", len, romparams[0], CartROMSize);
|
|
|
|
|
|
2017-10-10 16:01:05 -06:00
|
|
|
|
// generate a ROM ID
|
|
|
|
|
// note: most games don't check the actual value
|
|
|
|
|
// it just has to stay the same throughout gameplay
|
2018-12-12 12:59:08 -07:00
|
|
|
|
CartID = 0x000000C2;
|
|
|
|
|
|
|
|
|
|
if (CartROMSize <= 128*1024*1024)
|
|
|
|
|
CartID |= ((CartROMSize >> 20) - 1) << 8;
|
|
|
|
|
else
|
|
|
|
|
CartID |= (0x100 - (CartROMSize >> 28)) << 8;
|
|
|
|
|
|
|
|
|
|
if (romparams[1] == 8)
|
|
|
|
|
CartID |= 0x08000000; // NAND flag
|
|
|
|
|
|
|
|
|
|
printf("Cart ID: %08X\n", CartID);
|
2017-10-10 16:01:05 -06:00
|
|
|
|
|
2018-04-26 16:17:05 -06:00
|
|
|
|
if (*(u32*)&CartROM[0x20] < 0x4000)
|
|
|
|
|
{
|
2018-10-17 16:54:21 -06:00
|
|
|
|
//ApplyDLDIPatch();
|
2018-04-26 16:17:05 -06:00
|
|
|
|
}
|
|
|
|
|
|
2017-03-19 12:07:39 -06:00
|
|
|
|
if (direct)
|
|
|
|
|
{
|
2018-04-26 16:17:05 -06:00
|
|
|
|
// TODO: in the case of an already-encrypted secure area, direct boot
|
|
|
|
|
// needs it decrypted
|
2017-03-19 12:07:39 -06:00
|
|
|
|
NDS::SetupDirectBoot();
|
|
|
|
|
CmdEncMode = 2;
|
|
|
|
|
}
|
2017-02-01 13:35:00 -07:00
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
CartInserted = true;
|
|
|
|
|
|
2018-12-12 12:59:08 -07:00
|
|
|
|
// TODO: support more fancy cart types (homebrew?, flashcarts, etc)
|
|
|
|
|
if (CartID & 0x08000000)
|
|
|
|
|
ROMCommandHandler = ROMCommand_RetailNAND;
|
|
|
|
|
else
|
|
|
|
|
ROMCommandHandler = ROMCommand_Retail;
|
|
|
|
|
|
2017-01-22 18:26:05 -07:00
|
|
|
|
u32 arm9base = *(u32*)&CartROM[0x20];
|
|
|
|
|
if (arm9base < 0x8000)
|
|
|
|
|
{
|
|
|
|
|
if (arm9base >= 0x4000)
|
|
|
|
|
{
|
|
|
|
|
// reencrypt secure area if needed
|
2017-03-19 12:07:39 -06:00
|
|
|
|
if (*(u32*)&CartROM[arm9base] == 0xE7FFDEFF && *(u32*)&CartROM[arm9base+0x10] != 0xE7FFDEFF)
|
2017-01-22 18:26:05 -07:00
|
|
|
|
{
|
|
|
|
|
printf("Re-encrypting cart secure area\n");
|
|
|
|
|
|
|
|
|
|
strncpy((char*)&CartROM[arm9base], "encryObj", 8);
|
|
|
|
|
|
|
|
|
|
Key1_InitKeycode(gamecode, 3, 2);
|
|
|
|
|
for (u32 i = 0; i < 0x800; i += 8)
|
|
|
|
|
Key1_Encrypt((u32*)&CartROM[arm9base + i]);
|
|
|
|
|
|
|
|
|
|
Key1_InitKeycode(gamecode, 2, 2);
|
|
|
|
|
Key1_Encrypt((u32*)&CartROM[arm9base]);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
CartIsHomebrew = true;
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
// encryption
|
|
|
|
|
Key1_InitKeycode(gamecode, 2, 2);
|
2017-02-03 08:57:31 -07:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// save
|
2018-10-23 13:52:41 -06:00
|
|
|
|
printf("Save file: %s\n", sram);
|
2018-12-11 12:39:07 -07:00
|
|
|
|
NDSCart_SRAM::LoadSave(sram, romparams[1]);
|
2017-02-07 15:31:21 -07:00
|
|
|
|
|
|
|
|
|
return true;
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|
|
|
|
|
|
2018-10-23 16:24:36 -06:00
|
|
|
|
void RelocateSave(const char* path, bool write)
|
2018-10-23 14:54:09 -06:00
|
|
|
|
{
|
|
|
|
|
// herp derp
|
2018-10-23 16:24:36 -06:00
|
|
|
|
NDSCart_SRAM::RelocateSave(path, write);
|
2018-10-23 14:54:09 -06:00
|
|
|
|
}
|
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
void ReadROM(u32 addr, u32 len, u32 offset)
|
|
|
|
|
{
|
|
|
|
|
if (!CartInserted) return;
|
|
|
|
|
|
|
|
|
|
if (addr >= CartROMSize) return;
|
|
|
|
|
if ((addr+len) > CartROMSize)
|
|
|
|
|
len = CartROMSize - addr;
|
|
|
|
|
|
|
|
|
|
memcpy(DataOut+offset, CartROM+addr, len);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ReadROM_B7(u32 addr, u32 len, u32 offset)
|
|
|
|
|
{
|
2017-03-29 10:59:20 -06:00
|
|
|
|
if (!CartInserted) return;
|
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
addr &= (CartROMSize-1);
|
2017-01-22 18:26:05 -07:00
|
|
|
|
if (!CartIsHomebrew)
|
|
|
|
|
{
|
|
|
|
|
if (addr < 0x8000)
|
|
|
|
|
addr = 0x8000 + (addr & 0x1FF);
|
|
|
|
|
}
|
2017-01-22 12:34:59 -07:00
|
|
|
|
|
|
|
|
|
memcpy(DataOut+offset, CartROM+addr, len);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2017-04-11 12:21:31 -06:00
|
|
|
|
void ROMEndTransfer(u32 param)
|
2017-01-22 12:34:59 -07:00
|
|
|
|
{
|
|
|
|
|
ROMCnt &= ~(1<<31);
|
|
|
|
|
|
|
|
|
|
if (SPICnt & (1<<14))
|
2017-03-02 16:48:26 -07:00
|
|
|
|
NDS::SetIRQ((NDS::ExMemCnt[0]>>11)&0x1, NDS::IRQ_CartSendDone);
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ROMPrepareData(u32 param)
|
|
|
|
|
{
|
|
|
|
|
if (DataOutPos >= DataOutLen)
|
|
|
|
|
ROMDataOut = 0;
|
|
|
|
|
else
|
|
|
|
|
ROMDataOut = *(u32*)&DataOut[DataOutPos];
|
|
|
|
|
|
|
|
|
|
DataOutPos += 4;
|
|
|
|
|
|
|
|
|
|
ROMCnt |= (1<<23);
|
2017-04-27 10:45:43 -06:00
|
|
|
|
|
|
|
|
|
if (NDS::ExMemCnt[0] & (1<<11))
|
|
|
|
|
NDS::CheckDMAs(1, 0x12);
|
|
|
|
|
else
|
|
|
|
|
NDS::CheckDMAs(0, 0x05);
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|
|
|
|
|
|
2018-12-12 12:59:08 -07:00
|
|
|
|
|
|
|
|
|
void ROMCommand_Retail(u8* cmd)
|
|
|
|
|
{
|
|
|
|
|
switch (cmd[0])
|
|
|
|
|
{
|
|
|
|
|
case 0xB7:
|
|
|
|
|
{
|
|
|
|
|
u32 addr = (cmd[1]<<24) | (cmd[2]<<16) | (cmd[3]<<8) | cmd[4];
|
|
|
|
|
memset(DataOut, 0, DataOutLen);
|
|
|
|
|
|
|
|
|
|
if (((addr + DataOutLen - 1) >> 12) != (addr >> 12))
|
|
|
|
|
{
|
|
|
|
|
u32 len1 = 0x1000 - (addr & 0xFFF);
|
|
|
|
|
ReadROM_B7(addr, len1, 0);
|
|
|
|
|
ReadROM_B7(addr+len1, DataOutLen-len1, len1);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
ReadROM_B7(addr, DataOutLen, 0);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
printf("unknown retail cart command %02X\n", cmd[0]);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ROMCommand_RetailNAND(u8* cmd)
|
|
|
|
|
{
|
|
|
|
|
switch (cmd[0])
|
|
|
|
|
{
|
|
|
|
|
case 0x94: // NAND init
|
|
|
|
|
{
|
|
|
|
|
// initial value: should have bit7 clear
|
|
|
|
|
NDSCart_SRAM::StatusReg = 0;
|
|
|
|
|
|
|
|
|
|
// Jam with the Band stores words 6-9 of this at 0x02131BB0
|
|
|
|
|
// it doesn't seem to use those anywhere later
|
|
|
|
|
for (u32 pos = 0; pos < DataOutLen; pos += 4)
|
|
|
|
|
*(u32*)&DataOut[pos] = 0;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xB2: // set savemem addr
|
|
|
|
|
{
|
|
|
|
|
NDSCart_SRAM::StatusReg |= 0x20;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xB7:
|
|
|
|
|
{
|
|
|
|
|
u32 addr = (cmd[1]<<24) | (cmd[2]<<16) | (cmd[3]<<8) | cmd[4];
|
|
|
|
|
memset(DataOut, 0, DataOutLen);
|
|
|
|
|
|
|
|
|
|
if (((addr + DataOutLen - 1) >> 12) != (addr >> 12))
|
|
|
|
|
{
|
|
|
|
|
u32 len1 = 0x1000 - (addr & 0xFFF);
|
|
|
|
|
ReadROM_B7(addr, len1, 0);
|
|
|
|
|
ReadROM_B7(addr+len1, DataOutLen-len1, len1);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
ReadROM_B7(addr, DataOutLen, 0);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xD6: // NAND status
|
|
|
|
|
{
|
|
|
|
|
// status reg bits:
|
|
|
|
|
// * bit7: busy? error?
|
|
|
|
|
// * bit5: accessing savemem
|
|
|
|
|
|
|
|
|
|
for (u32 pos = 0; pos < DataOutLen; pos += 4)
|
|
|
|
|
*(u32*)&DataOut[pos] = NDSCart_SRAM::StatusReg * 0x01010101;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
printf("unknown NAND command %02X %04Xn", cmd[0], DataOutLen);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2018-04-27 12:00:53 -06:00
|
|
|
|
|
2017-01-31 09:34:17 -07:00
|
|
|
|
void WriteROMCnt(u32 val)
|
2018-04-27 12:00:53 -06:00
|
|
|
|
{
|
2017-04-11 12:21:31 -06:00
|
|
|
|
ROMCnt = (val & 0xFF7F7FFF) | (ROMCnt & 0x00800000);
|
2017-01-22 12:34:59 -07:00
|
|
|
|
|
|
|
|
|
if (!(SPICnt & (1<<15))) return;
|
|
|
|
|
|
|
|
|
|
if (val & (1<<15))
|
|
|
|
|
{
|
|
|
|
|
u32 snum = (NDS::ExMemCnt[0]>>8)&0x8;
|
|
|
|
|
u64 seed0 = *(u32*)&NDS::ROMSeed0[snum] | ((u64)NDS::ROMSeed0[snum+4] << 32);
|
|
|
|
|
u64 seed1 = *(u32*)&NDS::ROMSeed1[snum] | ((u64)NDS::ROMSeed1[snum+4] << 32);
|
|
|
|
|
|
|
|
|
|
Key2_X = 0;
|
|
|
|
|
Key2_Y = 0;
|
|
|
|
|
for (u32 i = 0; i < 39; i++)
|
|
|
|
|
{
|
|
|
|
|
if (seed0 & (1ULL << i)) Key2_X |= (1ULL << (38-i));
|
|
|
|
|
if (seed1 & (1ULL << i)) Key2_Y |= (1ULL << (38-i));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
printf("seed0: %02X%08X\n", (u32)(seed0>>32), (u32)seed0);
|
|
|
|
|
printf("seed1: %02X%08X\n", (u32)(seed1>>32), (u32)seed1);
|
|
|
|
|
printf("key2 X: %02X%08X\n", (u32)(Key2_X>>32), (u32)Key2_X);
|
|
|
|
|
printf("key2 Y: %02X%08X\n", (u32)(Key2_Y>>32), (u32)Key2_Y);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!(ROMCnt & (1<<31))) return;
|
|
|
|
|
|
|
|
|
|
u32 datasize = (ROMCnt >> 24) & 0x7;
|
|
|
|
|
if (datasize == 7)
|
|
|
|
|
datasize = 4;
|
|
|
|
|
else if (datasize > 0)
|
|
|
|
|
datasize = 0x100 << datasize;
|
|
|
|
|
|
|
|
|
|
DataOutPos = 0;
|
|
|
|
|
DataOutLen = datasize;
|
|
|
|
|
|
|
|
|
|
// handle KEY1 encryption as needed.
|
|
|
|
|
// KEY2 encryption is implemented in hardware and doesn't need to be handled.
|
|
|
|
|
u8 cmd[8];
|
|
|
|
|
if (CmdEncMode == 1)
|
|
|
|
|
{
|
|
|
|
|
*(u32*)&cmd[0] = ByteSwap(*(u32*)&ROMCommand[4]);
|
|
|
|
|
*(u32*)&cmd[4] = ByteSwap(*(u32*)&ROMCommand[0]);
|
|
|
|
|
Key1_Decrypt((u32*)cmd);
|
|
|
|
|
u32 tmp = ByteSwap(*(u32*)&cmd[4]);
|
|
|
|
|
*(u32*)&cmd[4] = ByteSwap(*(u32*)&cmd[0]);
|
|
|
|
|
*(u32*)&cmd[0] = tmp;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
*(u32*)&cmd[0] = *(u32*)&ROMCommand[0];
|
|
|
|
|
*(u32*)&cmd[4] = *(u32*)&ROMCommand[4];
|
|
|
|
|
}
|
|
|
|
|
|
2018-04-27 12:00:53 -06:00
|
|
|
|
/*printf("ROM COMMAND %04X %08X %02X%02X%02X%02X%02X%02X%02X%02X SIZE %04X\n",
|
2017-01-22 12:34:59 -07:00
|
|
|
|
SPICnt, ROMCnt,
|
|
|
|
|
cmd[0], cmd[1], cmd[2], cmd[3],
|
|
|
|
|
cmd[4], cmd[5], cmd[6], cmd[7],
|
2018-04-27 12:00:53 -06:00
|
|
|
|
datasize);*/
|
2017-01-22 12:34:59 -07:00
|
|
|
|
|
|
|
|
|
switch (cmd[0])
|
|
|
|
|
{
|
|
|
|
|
case 0x9F:
|
|
|
|
|
memset(DataOut, 0xFF, DataOutLen);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x00:
|
|
|
|
|
memset(DataOut, 0, DataOutLen);
|
|
|
|
|
if (DataOutLen > 0x1000)
|
|
|
|
|
{
|
|
|
|
|
ReadROM(0, 0x1000, 0);
|
|
|
|
|
for (u32 pos = 0x1000; pos < DataOutLen; pos += 0x1000)
|
|
|
|
|
memcpy(DataOut+pos, DataOut, 0x1000);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
ReadROM(0, DataOutLen, 0);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x90:
|
|
|
|
|
case 0xB8:
|
|
|
|
|
for (u32 pos = 0; pos < DataOutLen; pos += 4)
|
|
|
|
|
*(u32*)&DataOut[pos] = CartID;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x3C:
|
2017-03-29 10:59:20 -06:00
|
|
|
|
if (CartInserted) CmdEncMode = 1;
|
2017-01-22 12:34:59 -07:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
2018-12-12 12:59:08 -07:00
|
|
|
|
if (CmdEncMode == 1)
|
2017-01-22 12:34:59 -07:00
|
|
|
|
{
|
2018-12-12 12:59:08 -07:00
|
|
|
|
switch (cmd[0] & 0xF0)
|
2017-01-22 18:26:05 -07:00
|
|
|
|
{
|
2018-12-12 12:59:08 -07:00
|
|
|
|
case 0x40:
|
|
|
|
|
DataEncMode = 2;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x10:
|
|
|
|
|
for (u32 pos = 0; pos < DataOutLen; pos += 4)
|
|
|
|
|
*(u32*)&DataOut[pos] = CartID;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x20:
|
|
|
|
|
{
|
|
|
|
|
u32 addr = (cmd[2] & 0xF0) << 8;
|
|
|
|
|
ReadROM(addr, 0x1000, 0);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xA0:
|
|
|
|
|
CmdEncMode = 2;
|
|
|
|
|
break;
|
2017-01-22 18:26:05 -07:00
|
|
|
|
}
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|
2018-12-12 12:59:08 -07:00
|
|
|
|
else if (ROMCommandHandler)
|
|
|
|
|
ROMCommandHandler(cmd);
|
2017-01-22 12:34:59 -07:00
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2017-04-11 12:21:31 -06:00
|
|
|
|
ROMCnt &= ~(1<<23);
|
|
|
|
|
|
|
|
|
|
// ROM transfer timings
|
|
|
|
|
// the bus is parallel with 8 bits
|
|
|
|
|
// thus a command would take 8 cycles to be transferred
|
|
|
|
|
// and it would take 4 cycles to receive a word of data
|
2017-04-27 10:45:43 -06:00
|
|
|
|
// TODO: advance read position if bit28 is set
|
2017-01-22 12:34:59 -07:00
|
|
|
|
|
2017-04-11 12:21:31 -06:00
|
|
|
|
u32 xfercycle = (ROMCnt & (1<<27)) ? 8 : 5;
|
2017-04-24 18:26:37 -06:00
|
|
|
|
u32 cmddelay = 8 + (ROMCnt & 0x1FFF);
|
2017-04-27 10:45:43 -06:00
|
|
|
|
if (datasize) cmddelay += ((ROMCnt >> 16) & 0x3F);
|
2017-04-24 18:26:37 -06:00
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
if (datasize == 0)
|
2017-04-24 18:26:37 -06:00
|
|
|
|
NDS::ScheduleEvent(NDS::Event_ROMTransfer, false, xfercycle*cmddelay, ROMEndTransfer, 0);
|
2017-01-22 12:34:59 -07:00
|
|
|
|
else
|
2017-04-24 18:26:37 -06:00
|
|
|
|
NDS::ScheduleEvent(NDS::Event_ROMTransfer, true, xfercycle*(cmddelay+4), ROMPrepareData, 0);
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|
|
|
|
|
|
2017-01-31 09:34:17 -07:00
|
|
|
|
u32 ReadROMData()
|
2017-01-22 12:34:59 -07:00
|
|
|
|
{
|
2017-04-11 12:21:31 -06:00
|
|
|
|
if (ROMCnt & (1<<23))
|
2017-01-22 12:34:59 -07:00
|
|
|
|
{
|
|
|
|
|
ROMCnt &= ~(1<<23);
|
|
|
|
|
|
2017-04-11 12:21:31 -06:00
|
|
|
|
if (DataOutPos < DataOutLen)
|
|
|
|
|
{
|
|
|
|
|
u32 xfercycle = (ROMCnt & (1<<27)) ? 8 : 5;
|
2017-04-24 18:26:37 -06:00
|
|
|
|
u32 delay = 4;
|
|
|
|
|
if (!(DataOutPos & 0x1FF)) delay += ((ROMCnt >> 16) & 0x3F);
|
|
|
|
|
|
|
|
|
|
NDS::ScheduleEvent(NDS::Event_ROMTransfer, true, xfercycle*delay, ROMPrepareData, 0);
|
2017-04-11 12:21:31 -06:00
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
ROMEndTransfer(0);
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|
|
|
|
|
|
2017-04-11 12:21:31 -06:00
|
|
|
|
return ROMDataOut;
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|
|
|
|
|
|
2017-01-31 09:34:17 -07:00
|
|
|
|
|
|
|
|
|
void WriteSPICnt(u16 val)
|
|
|
|
|
{
|
|
|
|
|
SPICnt = (SPICnt & 0x0080) | (val & 0xE043);
|
2017-07-15 11:29:10 -06:00
|
|
|
|
if (SPICnt & (1<<7))
|
|
|
|
|
printf("!! CHANGING AUXSPICNT DURING TRANSFER: %04X\n", val);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void SPITransferDone(u32 param)
|
|
|
|
|
{
|
|
|
|
|
SPICnt &= ~(1<<7);
|
2017-01-31 09:34:17 -07:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
u8 ReadSPIData()
|
|
|
|
|
{
|
|
|
|
|
if (!(SPICnt & (1<<15))) return 0;
|
|
|
|
|
if (!(SPICnt & (1<<13))) return 0;
|
2017-07-15 11:29:10 -06:00
|
|
|
|
if (SPICnt & (1<<7)) return 0; // checkme
|
2017-01-31 09:34:17 -07:00
|
|
|
|
|
|
|
|
|
return NDSCart_SRAM::Read();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void WriteSPIData(u8 val)
|
|
|
|
|
{
|
|
|
|
|
if (!(SPICnt & (1<<15))) return;
|
|
|
|
|
if (!(SPICnt & (1<<13))) return;
|
|
|
|
|
|
2017-07-15 11:29:10 -06:00
|
|
|
|
if (SPICnt & (1<<7)) printf("!! WRITING AUXSPIDATA DURING PENDING TRANSFER\n");
|
2017-01-31 09:34:17 -07:00
|
|
|
|
|
2017-07-15 11:29:10 -06:00
|
|
|
|
SPICnt |= (1<<7);
|
2017-01-31 09:34:17 -07:00
|
|
|
|
NDSCart_SRAM::Write(val, SPICnt&(1<<6));
|
2017-07-15 11:29:10 -06:00
|
|
|
|
|
|
|
|
|
// SPI transfers one bit per cycle -> 8 cycles per byte
|
|
|
|
|
u32 delay = 8 * (8 << (SPICnt & 0x3));
|
|
|
|
|
NDS::ScheduleEvent(NDS::Event_ROMSPITransfer, false, delay, SPITransferDone, 0);
|
2017-01-31 09:34:17 -07:00
|
|
|
|
}
|
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|